From: Thiemo Seufer Date: Tue, 9 Jul 2002 14:21:40 +0000 (+0000) Subject: * config/tc-mips.c (macro_build): Handle MIPS16 insns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aec421e08bbb6921022f45cf5f19a194177f2afb;p=binutils-gdb.git * config/tc-mips.c (macro_build): Handle MIPS16 insns. (mips_ip): Likewise. * mips.h (INSN_MIPS16): New define. * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. * mips-opc.c (I16): New define. (mips_builtin_opcodes): Make jalx an I16 insn. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index dd26b0b8e62..a825704ad64 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2002-07-09 Thiemo Seufer + + * config/tc-mips.c (macro_build): Handle MIPS16 insns. + (mips_ip): Likewise. + 2002-07-09 Alan Modra * config/tc-i386.c (md_pseudo_table ): Warning fix. diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index ba4480cb4ab..2b88e5694ba 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2728,7 +2728,10 @@ macro_build (place, counter, ep, name, fmt, va_alist) MDMX or MIPS-3D instructions. */ if (strcmp (fmt, insn.insn_mo->args) == 0 && insn.insn_mo->pinfo != INSN_MACRO - && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch) + && OPCODE_IS_MEMBER (insn.insn_mo, + (mips_opts.isa + | (mips_opts.mips16 ? INSN_MIPS16 : 0)), + mips_arch) && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0)) break; @@ -7733,6 +7736,7 @@ mips_ip (str, ip) if (OPCODE_IS_MEMBER (insn, (mips_opts.isa + | (mips_opts.mips16 ? INSN_MIPS16 : 0) | (mips_opts.ase_mdmx ? INSN_MDMX : 0) | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)), mips_arch)) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index f771d86f67d..385b1915298 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2002-07-09 Thiemo Seufer + + * mips.h (INSN_MIPS16): New define. + 2002-07-08 Alan Modra * i386.h: Remove IgnoreSize from movsx and movzx. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 801999c05c8..312a2ac1717 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -339,7 +339,10 @@ struct mips_opcode #define INSN_ISA64 0x00000400 /* Masks used for MIPS-defined ASEs. */ +#define INSN_ASE_MASK 0x0000f000 +/* MIPS 16 ASE */ +#define INSN_MIPS16 0x00002000 /* MIPS-3D ASE */ #define INSN_MIPS3D 0x00004000 /* MDMX ASE */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0b8925b25a1..5cba4ec4b32 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2002-07-09 Thiemo Seufer + + * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. + * mips-opc.c (I16): New define. + (mips_builtin_opcodes): Make jalx an I16 insn. + 2002-06-18 Dave Brolley * po/POTFILES.in: Add frv-*.[ch]. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index b832ca2ce45..9b35a472712 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -412,7 +412,7 @@ mips_isa_type (mach, isa, cputype) break; case bfd_mach_mips16: *cputype = CPU_MIPS16; - *isa = ISA_MIPS3; + *isa = ISA_MIPS3 | INSN_MIPS16; break; case bfd_mach_mips5: *cputype = CPU_MIPS5; @@ -429,12 +429,12 @@ mips_isa_type (mach, isa, cputype) _MIPS32 Architecture For Programmers Volume I: Introduction to the MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), page 1. */ - *isa = ISA_MIPS32; + *isa = ISA_MIPS32 | INSN_MIPS16; break; case bfd_mach_mipsisa64: *cputype = CPU_MIPS64; /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ - *isa = ISA_MIPS64 | INSN_MDMX | INSN_MIPS3D; + *isa = ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX; break; default: diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index cbf92230a9a..7edda058053 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -86,6 +86,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define I32 INSN_ISA32 #define I64 INSN_ISA64 +/* MIPS64 MIPS-3D ASE support. */ +#define I16 INSN_MIPS16 + /* MIPS64 MIPS-3D ASE support. */ #define M3D INSN_MIPS3D @@ -568,9 +571,7 @@ const struct mips_opcode mips_builtin_opcodes[] = assembler, but will never match user input (because the line above will match first). */ {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, - /* jalx really should only be avaliable if mips16 is available, - but for now make it I1. */ -{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I16 }, {"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */ {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },