From: lkcl <lkcl@web>
Date: Sun, 25 Sep 2022 09:39:56 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~284
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aee587e6b4906294f52cb00b5b4e88786bfe3cbe;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index a689cf478..bc9985438 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -16,7 +16,7 @@ possibility of MSB0 numbering being potentially applicable to:
 * register numbers
 * element numbers
 
-In other words, when communicating in a Specification there are **four**
+In other words, when communicating in a Specification there are **eight**
 possible areas for confusion.
 
 Then there is the completely separate issue of whether:
@@ -29,8 +29,10 @@ Then there is the completely separate issue of whether:
   reordering over Memory **and the bytes inside regfile data**
   needs provided at the ISA Level.
 
-This leaves a combinatorial explosion in the potential for confusion
-in communication, leading to utter chaos.
+The latter introduces at least another four potential areas for
+reordering, leading to a combinatorial explosion in the potential for
+confusion
+in communication, causing utter chaos and a proliferation of complexity.
 
 Simple-V has made the decision that providing programmers with explicit
 control over the byte-ordering when data is transferred in and out of