From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Jul 2020 22:15:55 +0000 (+0100)
Subject: add mul unit to test_issuer
X-Git-Tag: div_pipeline~162^2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aeea9fb1c80668de6057fa919b6eeb4bf4790a51;p=soc.git

add mul unit to test_issuer
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 9feafaf1..e787df5f 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -163,6 +163,7 @@ class TestIssuer(Elaboratable):
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',