From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 Jul 2020 19:15:23 +0000 (+0100)
Subject: adding in ALU test back in, debugging SPR setup
X-Git-Tag: div_pipeline~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aefc1dab6fdcd7e555b8a3fdc07cb1e801b58bbe;p=soc.git

adding in ALU test back in, debugging SPR setup
---

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
index dff63be8..536c16fb 100644
--- a/src/soc/regfile/util.py
+++ b/src/soc/regfile/util.py
@@ -1,5 +1,5 @@
 from soc.regfile.regfiles import FastRegs
-from soc.decoder.power_enums import SPR
+from soc.decoder.power_enums import SPR, spr_dict
 
 def fast_reg_to_spr(spr_num):
     if spr_num == FastRegs.CTR:
diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index d3599be8..aa1845e7 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -14,7 +14,7 @@ from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.isa.all import ISA
-from soc.decoder.power_enums import Function, XER_bits
+from soc.decoder.power_enums import SPR, Function, XER_bits
 from soc.config.test.test_loadstore import TestMemPspec
 
 from soc.simple.core import NonProductionCore
diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 1159a85d..b91c1dde 100644
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -25,7 +25,7 @@ from soc.fu.compunits.test.test_compunit import (setup_test_memory,
                                                  check_sim_memory)
 
 # test with ALU data and Logical data
-#from soc.fu.alu.test.test_pipe_caller import ALUTestCase
+from soc.fu.alu.test.test_pipe_caller import ALUTestCase
 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
@@ -186,7 +186,7 @@ if __name__ == "__main__":
     #suite.addTest(TestRunner(CRTestCase.test_data))
     #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
     #suite.addTest(TestRunner(LogicalTestCase.test_data))
-    #suite.addTest(TestRunner(ALUTestCase.test_data))
+    suite.addTest(TestRunner(ALUTestCase.test_data))
     #suite.addTest(TestRunner(BranchTestCase.test_data))
     suite.addTest(TestRunner(SPRTestCase.test_data))