From: Michael Nolan <mtnolan2640@gmail.com>
Date: Tue, 19 May 2020 19:59:33 +0000 (-0400)
Subject: Add should_trap signal to trap output data
X-Git-Tag: div_pipeline~1068
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af05977b396dbf5d088c7b9b3276d40806b626bb;p=soc.git

Add should_trap signal to trap output data
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index e5771b17..7fcdc177 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -78,9 +78,14 @@ class LogicalMainStage(PipeModBase):
             
         with m.Switch(op):
             with m.Case(InternalOp.OP_TRAP):
-                pass
+                with m.If(should_trap):
+                    comb += self.o.nia.eq(0x700)
+                    comb += self.o.srr1.eq(self.i.msr)
+                    comb += self.o.srr1[63-46].eq(1)
+                    comb += self.o.srr0.eq(self.i.cia)
 
 
         comb += self.o.ctx.eq(self.i.ctx)
+        comb += self.o.should_trap.eq(should_trap)
 
         return m
diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 42548952..751a1835 100644
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -30,6 +30,7 @@ class TrapOutputData(IntegerData):
         self.msr = Signal(64, reset_less=True) # RB/immediate
         self.srr0 = Signal(64, reset_less=True) # RB/immediate
         self.srr1 = Signal(64, reset_less=True) # RB/immediate
+        self.should_trap = Signal(reset_less=True)
 
     def __iter__(self):
         yield from super().__iter__()
@@ -37,9 +38,11 @@ class TrapOutputData(IntegerData):
         yield self.msr
         yield self.srr0
         yield self.srr1
+        yield self.should_trap
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [
             self.nia.eq(i.nia), self.msr.eq(i.msr),
-            self.srr0.eq(i.srr0), self.srr1.eq(i.srr1)]
+            self.srr0.eq(i.srr0), self.srr1.eq(i.srr1),
+            self.should_trap.eq(i.should_trap)]