From: lkcl Date: Tue, 3 May 2022 16:35:21 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2504 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af08a81327dbc6da698dd51e63b7dfc290312b00;p=libreriscv.git --- diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 4dc08e0ea..850a11e95 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -98,13 +98,10 @@ TODO: convert all instructions to use RT and not RS | NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog | | NN | | | | | ..... 01 |0 | crternlog | | NN | RT | RA | RB | RC | mode 010 |Rc| bitmask* | -| NN | RS | RA | RB | RC | 00 011 |0 | gfbmadd | -| NN | RS | RA | RB | RC | 00 011 |1 | gfbmaddsub | -| NN | RS | RA | RB | RC | 01 011 |0 | clmadd | -| NN | RS | RA | RB | RC | 01 011 |1 | clmaddsub | -| NN | RS | RA | RB | RC | 10 011 |0 | gfpmadd | -| NN | RS | RA | RB | RC | 10 011 |1 | gfpmaddsub | -| NN | RS | RA | RB | RC | 11 011 | | rsvd | +| NN | | | | | 00 011 | | rsvd | +| NN | | | | | 01 011 | | rsvd | +| NN | | | | | 10 011 | | rsvd | +| NN | | | | | 11 011 |Rc| setvl | | NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi | ops (note that av avg and abs as well as vec scalar mask @@ -126,13 +123,13 @@ double check that instructions didn't need 3 inputs. | NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm | | NN | RA | RB | RC | 0 | 10 | 0001 110 |Rc| vec sifm | | NN | RA | RB | RC | 0 | 11 | 0001 110 |Rc| vec cprop | +| NN | RT | RA | RB | 0 | | 0101 110 |Rc| rsvd | | NN | RT | RA | RB | 1 | itype | 0101 110 |Rc| xperm | -| NN | RA | RB | RC | 0 | itype | 0101 110 |Rc| av minmax | -| NN | RA | RB | RC | 1 | 00 | 0101 110 |Rc| av abss | -| NN | RA | RB | RC | 1 | 01 | 0101 110 |Rc| av absu| -| NN | RA | RB | | 1 | 10 | 0101 110 |Rc| av avgadd | -| NN | RA | RB | | 1 | 11 | 0101 110 |Rc| rsvd | -| NN | RA | RB | | | | 1001 110 |Rc| rsvd | +| NN | RA | RB | RC | 0 | itype | 1001 110 |Rc| av minmax | +| NN | RA | RB | RC | 1 | 00 | 1001 110 |Rc| av abss | +| NN | RA | RB | RC | 1 | 01 | 1001 110 |Rc| av absu| +| NN | RA | RB | | 1 | 10 | 1001 110 |Rc| av avgadd | +| NN | RA | RB | | 1 | 11 | 1001 110 |Rc| rsvd | | NN | RA | RB | | | | 1101 110 |Rc| rsvd | | NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc | | NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci | @@ -148,7 +145,7 @@ double check that instructions didn't need 3 inputs. | NN | RA | RB | RC | | 10 | --10 110 |Rc| rsvd | | NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr | | NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh | -| NN | | | | | | --11 110 |Rc| setvl | +| NN | | | | | | --11 110 |Rc| rsvd | # ternlog bitops