From: lkcl <lkcl@web>
Date: Fri, 24 Nov 2023 21:46:34 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af0c6bb030fb0d701a8d8399b0d6aead1977a564;p=libreriscv.git

---

diff --git a/meetings/dmitry_2023-11-24.mdwn b/meetings/dmitry_2023-11-24.mdwn
index 6616c2d3b..55954356c 100644
--- a/meetings/dmitry_2023-11-24.mdwn
+++ b/meetings/dmitry_2023-11-24.mdwn
@@ -62,7 +62,7 @@ For both RISC-V and PowerISA need to define:
 - SVP64Single
 
 *(Andrey: Why do these need to be defined for PowerISA?
-To also save on instruction memory?)*
+A: see page and bugreport. full 128 reg access)*
 
 Doing this work for both ISAs at the same time isn't too difficult,
 as the SVPxxSingle format will be the same for both ISAs.