From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 20 Nov 2019 22:30:56 +0000 (-0800)
Subject: Add blackbox model for $__ABC9_FF_ so that clock partitioning works
X-Git-Tag: working-ls180~881^2^2~164
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af3055fe8354e0a082bd8415448fcbeb5ee435f6;p=yosys.git

Add blackbox model for $__ABC9_FF_ so that clock partitioning works
---

diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index c17d6744a..cc0e5ec41 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -30,6 +30,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
 (* abc_box_id = 1000 *)
 module \$__ABC9_ASYNC (input A, S, output Y);
 endmodule