From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Mar 2019 02:54:57 +0000 (+0000)
Subject: update comments
X-Git-Tag: ls180-24jan2020~1673
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af3ae7902ba4e5a26556eb4442c8351c95b267a4;p=ieee754fpu.git

update comments
---

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 6bd4d062..6678a671 100644
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -181,7 +181,7 @@ class BufferedPipeline:
                ]
 
 
-class BufPipe(BufferedPipeline, ExampleStage):
+class BufPipe(BufferedPipeline):
 
     def __init__(self):
         BufferedPipeline.__init__(self)
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index f53037d1..1c795fc2 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -98,7 +98,6 @@ class InputGroup:
         pe = PriorityEncoder(self.num_rows)
         m.submodules.selector = pe
         m.submodules.out_op = self.out_op
-        m.submodules.out_op_v = self.out_op.v
         m.submodules += self.rs
 
         # connect priority encoder
@@ -822,7 +821,7 @@ class FPAddStage1Mod(FPState):
         #m.submodules.norm1_in_z = self.in_z
         #m.submodules.norm1_out_z = self.out_z
         m.d.comb += self.out_z.copy(self.in_z)
-        # tot[27] gets set when the sum overflows. shift result down
+        # tot[-1] (MSB) gets set when the sum overflows. shift result down
         with m.If(self.in_tot[-1]):
             m.d.comb += [
                 self.out_z.m.eq(self.in_tot[4:]),
@@ -832,7 +831,7 @@ class FPAddStage1Mod(FPState):
                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
                 self.out_z.e.eq(self.in_z.e + 1)
         ]
-        # tot[27] zero case
+        # tot[-1] (MSB) zero case
         with m.Else():
             m.d.comb += [
                 self.out_z.m.eq(self.in_tot[3:]),