From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Jan 2024 11:31:32 +0000 (+0000)
Subject: bug 1244: do cmpi example instead of add
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af5148eaedf98a2a41ef657e7e2b15f2e34c441e;p=libreriscv.git

bug 1244: do cmpi example instead of add
---

diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex
index bf95fb01b..a76f7e537 100644
--- a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex
+++ b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex
@@ -108,27 +108,25 @@
 
 
 \begin{frame}[fragile]
-\frametitle{Simple-V ADD in a nutshell}
+\frametitle{Simple-V CMPI in a nutshell}
 
 \begin{semiverbatim}
-function op\_add(rd, rs1, rs2, predr) # add not VADD!
-  int i, id=0, irs1=0, irs2=0;
+function op\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
+  int i, id=0, ira=0;
   for (i = 0; i < VL; i++)
-    if (ireg[predr] & 1<<i) # predication uses intregs
-       ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
-    if (reg\_is\_vectorised[rd] )  \{ id += 1; \}
-    if (reg\_is\_vectorised[rs1])  \{ irs1 += 1; \}
-    if (reg\_is\_vectorised[rs2])  \{ irs2 += 1; \}
+    CR[BA+id] <= compare(ireg[RA+ira], SI);
+    if (reg\_is\_vectorised[BA] ) \{ id += 1; \}
+    if (reg\_is\_vectorised[RA])  \{ ira += 1; \}
 \end{semiverbatim}
 
   \begin{itemize}
-   \item Above is oversimplified: Reg. indirection left out (for clarity).
-   \item SIMD slightly more complex (case above is elwidth = default)
+   \item Above is oversimplified: predication etc. left out
    \item Scalar-scalar and scalar-vector and vector-vector now all in one
-   \item OoO may choose to push ADDs into instr. queue (v. busy!)
+   \item OoO may choose to push CMPIs into instr. queue (v. busy!)
   \end{itemize}
 \end{frame}
 
+
 \frame{\frametitle{Additional Simple-V features}
 
  \begin{itemize}