From: Luke Kenneth Casson Leighton Date: Sat, 22 Oct 2022 16:32:41 +0000 (+0100) Subject: argh, extremely annoying: 4-operand dsld/dsrd is not possible to X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af551f02d2225fce57ae729a574ed4bf5ba83103;p=openpower-isa.git argh, extremely annoying: 4-operand dsld/dsrd is not possible to have EXTRA3, therefore it fails as a bigint operation. reverting --- diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn index b3728bf5..bb9ffc6e 100644 --- a/openpower/isa/svfixedarith.mdwn +++ b/openpower/isa/svfixedarith.mdwn @@ -48,16 +48,30 @@ Special Registers Altered: # [DRAFT] Double-width Shift Left Doubleword -VA2-Form +Z23-Form -* dsld RT,RA,RB,RC (Rc=0) -* dsld. RT,RA,RB,RC (Rc=1) +* dsld RT,RA,RB,sm (Rc=0) +* dsld. RT,RA,RB,sm (Rc=1) Pseudo-code: - hi <- (RC) - lo <- (RA) - sh <- (RB) + switch(sm) + case(0): + hi <- (RT) + lo <- (RA) + sh <- (RB) + case(1): + hi <- (RA) + lo <- (RT) + sh <- (RB) + case(2): + hi <- (RA) + lo <- (RB) + sh <- (RT) + default: + hi <- [0] * 64 + lo <- (RA) + sh <- (RB) n <- sh[58:63] mask[0:63] <- MASK(n, 63) v[0:63] <- (hi & mask) | (lo & ¬mask) @@ -69,16 +83,30 @@ Special Registers Altered: # [DRAFT] Double-width Shift Right Doubleword -VA2-Form +Z23-Form -* dsrd RT,RA,RB,RC (Rc=0) -* dsrd. RT,RA,RB,RC (Rc=1) +* dsrd RT,RA,RB,sm (Rc=0) +* dsrd. RT,RA,RB,sm (Rc=1) Pseudo-code: - hi <- (RC) - lo <- (RA) - sh <- (RB) + switch(sm) + case(0): + hi <- (RT) + lo <- (RA) + sh <- (RB) + case(1): + hi <- (RA) + lo <- (RT) + sh <- (RB) + case(2): + hi <- (RA) + lo <- (RB) + sh <- (RT) + default: + hi <- (RA) + lo <- [0] * 64 + sh <- (RB) n <- sh[58:63] mask[0:63] <- MASK(0, 63 - n) v[0:63] <- (hi & ¬mask) | (lo & mask) diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 5c0c41c3..2e8a32c9 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -43,6 +43,7 @@ slw,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0 sld,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0 and,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 subf,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 andc,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 mulhd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 addg6s,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 @@ -50,16 +51,19 @@ mulhw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 nor,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 subfe,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 adde,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 mulld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 mullw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 add,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 eqv,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 +dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 xor,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 divdeu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divweu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 orc,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 divde,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwe,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 or,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,RS,RB,0,RA,0,CR0,0 divdu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 @@ -73,19 +77,23 @@ mulhwu,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 srw,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0 srd,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0 subfo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 mulhd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 mulhw,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 subfeo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 addeo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 mulldo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 mullwo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 addo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 sraw,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0 srad,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RB,s:RS,0,0,RB,RS,RA,0,CR0,0 +dsld,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdeuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divweuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdeo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divweo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 +dsrd,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divduo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divwuo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 divdo,NORMAL,,1P,EXTRA3,NO,d:RT;d:CR0,s:RA,s:RB,0,RA,RB,0,RT,0,CR0,0 diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index 09eebc6a..31105cf7 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -38,10 +38,6 @@ maddld,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 -dsld,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 -dsld,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 -dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 -dsrd,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 pcdec,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,CR0,0 ternlogi,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 ffmsubs,NORMAL,,1P,EXTRA2,NO,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index 22c11cd2..f035b438 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -271,6 +271,7 @@ | PO | FRT | TE | FRB |RMC| XO |Rc | | PO | FRTp| TE | FRBp |RMC| XO |Rc | | PO | FRT | FRA | FRB |RMC| XO |Rc | + | PO | RT | RA | RB |sm | XO |Rc | | PO | RT | RA | RB |CY | XO |Rc | | PO | FRTp| FRA | FRBp |RMC| XO |Rc | | PO | FRTp| FRAp | FRBp |RMC| XO |Rc | @@ -787,6 +788,9 @@ SCi (11:31) SV Context Propagation immediate bitfield Formats: SVC + sm (21:22) + Immediate field used for selecting operands (shift mode) + Formats: Z23 SRb (11:14) SV REMAP byte-reversal field. Formats: SVC diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv index e4dd1ce4..1c67cbe7 100644 --- a/openpower/isatables/minor_31.csv +++ b/openpower/isatables/minor_31.csv @@ -208,3 +208,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 0b1000110110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tlbsync,X,,, 0b0000011110,ALU,OP_NOP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,wait,X,,, 0b0100111100,LOGICAL,OP_XOR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,xor,X,,, +0b0000111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b0100111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b1000111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b1100111001,SHIFT_ROT,OP_DSHL,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b0010111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b0110111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b1010111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0b1110111001,SHIFT_ROT,OP_DSHR,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,Z23,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv index b2426340..7d338877 100644 --- a/openpower/isatables/minor_4.csv +++ b/openpower/isatables/minor_4.csv @@ -7,7 +7,3 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,, 58,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg -52,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg -53,SHIFT_ROT,OP_DSHL,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsld,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg -54,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg -55,SHIFT_ROT,OP_DSHR,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,dsrd,VA2,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index f37d5a6b..56553e01 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -587,25 +587,25 @@ def va_form(fields, XO): @_custom_insns( - _insn("dsld", XO=26, Rc=0), # minor_4=52 (26<<1 | Rc=0) - _insn("dsld.", XO=26, Rc=1), # minor_4=53 (26<<1 | Rc=1) - _insn("dsrd", XO=27, Rc=0), # minor_4=54 (27<<1 | Rc=0) - _insn("dsrd.", XO=27, Rc=1), # minor_4=55 (27<<1 | Rc=1) + _insn("dsld", XO=0b00111001, Rc=0), + _insn("dsld.", XO=0b00111001, Rc=1), + _insn("dsrd", XO=0b10111001, Rc=0), + _insn("dsrd.", XO=0b10111001, Rc=1), ) def dsld_dsrd(fields, XO, Rc): # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG - # 1.6.21.1 VA2-FORM - # |0 |6 |11 |16 |21 |26 |31| - # | PO | RT | RA | RB | RC | XO |Rc| - PO = 4 - (RT, RA, RB, RC) = fields + # 1.6.27 Z23-FORM + # |0 |6 |11 |15 |16 |21 |23 |31 | + # | PO | RT | RA | RB |sm | XO |Rc | + PO = 31 + (RT, RA, RB, sm) = fields return instruction( (PO, 0, 5), (RT, 6, 10), (RA, 11, 15), (RB, 16, 20), - (RC, 21, 25), - (XO, 26, 30), + (sm, 21, 22), + (XO, 23, 30), (Rc, 31, 31), ) diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 662871b2..dafd6024 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -399,14 +399,14 @@ class SVSTATETestCase(unittest.TestCase): def test_29_dsld_dsrd(self): expected = [ - "dsld 5,4,5,3", - "dsrd 5,4,5,3", + "dsld 5,4,5,1", + "dsrd 5,4,5,2", "dsld. 5,4,5,3", - "dsrd. 5,4,5,3", - "sv.dsld *6,4,5,3", - "sv.dsrd *6,4,5,3", - "sv.dsld. *6,4,5,3", - "sv.dsrd. *6,4,5,3", + "dsrd. 5,4,5,0", + "sv.dsld *5,4,5,1", + "sv.dsrd *5,4,5,2", + "sv.dsld. *5,4,5,3", + "sv.dsrd. *5,4,5,0", ] self._do_tst(expected) diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index 6a314212..b6d86322 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -34,7 +34,7 @@ class BigIntCases(TestAccumulatorBase): # FIXME: test more divmod2du special cases def case_dsld0(self): - prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False) + prog = Program(list(SVP64Asm(["dsld 3,4,5,0"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -48,7 +48,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsld1(self): - prog = Program(list(SVP64Asm(["dsld 3,3,5,4"])), False) + prog = Program(list(SVP64Asm(["dsld 3,4,5,1"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -62,7 +62,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsld2(self): - prog = Program(list(SVP64Asm(["dsld 3,5,3,4"])), False) + prog = Program(list(SVP64Asm(["dsld 3,4,5,2"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -75,8 +75,22 @@ class BigIntCases(TestAccumulatorBase): e.intregs[3] = (v >> 64) % 2 ** 64 self.add_case(prog, gprs, expected=e) + def case_dsld3(self): + prog = Program(list(SVP64Asm(["dsld 3,4,5,3"])), False) + for sh in _SHIFT_TEST_RANGE: + with self.subTest(sh=sh): + gprs = [0] * 32 + gprs[3] = 0x123456789ABCDEF + gprs[4] = 0xFEDCBA9876543210 + gprs[5] = sh % 2 ** 64 + e = ExpectedState(pc=4, int_regs=gprs) + v = gprs[4] + v <<= sh % 64 + e.intregs[3] = (v >> 64) % 2 ** 64 + self.add_case(prog, gprs, expected=e) + def case_dsrd0(self): - prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,4,5,0"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -90,7 +104,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsrd1(self): - prog = Program(list(SVP64Asm(["dsrd 3,3,5,4"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,4,5,1"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -104,7 +118,7 @@ class BigIntCases(TestAccumulatorBase): self.add_case(prog, gprs, expected=e) def case_dsrd2(self): - prog = Program(list(SVP64Asm(["dsrd 3,5,3,4"])), False) + prog = Program(list(SVP64Asm(["dsrd 3,4,5,2"])), False) for sh in _SHIFT_TEST_RANGE: with self.subTest(sh=sh): gprs = [0] * 32 @@ -117,6 +131,20 @@ class BigIntCases(TestAccumulatorBase): e.intregs[3] = v % 2 ** 64 self.add_case(prog, gprs, expected=e) + def case_dsrd3(self): + prog = Program(list(SVP64Asm(["dsrd 3,4,5,3"])), False) + for sh in _SHIFT_TEST_RANGE: + with self.subTest(sh=sh): + gprs = [0] * 32 + gprs[3] = 0x123456789ABCDEF + gprs[4] = 0xFEDCBA9876543210 + gprs[5] = sh % 2 ** 64 + e = ExpectedState(pc=4, int_regs=gprs) + v = gprs[4] << 64 + v >>= sh % 64 + e.intregs[3] = v % 2 ** 64 + self.add_case(prog, gprs, expected=e) + class SVP64BigIntCases(TestAccumulatorBase): def case_sv_bigint_add(self):