From: Clifford Wolf Date: Thu, 28 Feb 2013 12:59:49 +0000 (+0100) Subject: Added online help for "show" and "hierarchy" commands X-Git-Tag: yosys-0.2.0~776 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af561800edc1d98c33fe057d5c02898460c9d6b9;p=yosys.git Added online help for "show" and "hierarchy" commands --- diff --git a/kernel/show.cc b/kernel/show.cc index d7da62cd2..eef4c44f8 100644 --- a/kernel/show.cc +++ b/kernel/show.cc @@ -298,7 +298,22 @@ struct ShowWorker }; struct ShowPass : public Pass { - ShowPass() : Pass("show") { } + ShowPass() : Pass("show", "generate schematics using graphviz") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" show [-viewer ] [selection]\n"); + log("\n"); + log("Create a graphviz DOT file for the selected part of the design and compile it\n"); + log("to a postscript file.\n"); + log("\n"); + log(" -viewer \n"); + log(" Also run the specified command with the postscript file as parameter.\n"); + log("\n"); + log("The generated output files are `yosys-show.dot' and `yosys-show.ps'.\n"); + log("\n"); + } virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Generating Graphviz representation of design.\n"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index c8cd77a16..9ba1594df 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -139,7 +139,30 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top) } struct HierarchyPass : public Pass { - HierarchyPass() : Pass("hierarchy") { } + HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" hierarchy [-check] [-top ]\n"); + log("\n"); + log("In parametric designs, a module might exists in serveral variations with\n"); + log("different parameter values. This pass looks at all modules in the current\n"); + log("design an re-runs the language frontends for the parametric modules as\n"); + log("needed.\n"); + log("\n"); + log(" -check\n"); + log(" also check the design hierarchy. this generates an error when\n"); + log(" an unknown module is used as cell type.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified top module to built a design hierarchy. modules\n"); + log(" outside this tree (unused modules) are removed.\n"); + log("\n"); + log("This pass ignores the current selection and always operates on all modules\n"); + log("in the current design.\n"); + log("\n"); + } virtual void execute(std::vector args, RTLIL::Design *design) { log_header("Executing HIERARCHY pass (removing modules outside design hierarchy).\n"); @@ -165,9 +188,8 @@ struct HierarchyPass : public Pass { log_cmd_error("Module `%s' not found!\n", args[argidx].c_str()); continue; } - break; + log_cmd_error("Unkown option %s.\n", args[argidx].c_str()); } - extra_args(args, argidx, design); if (top_mod != NULL) hierarchy(design, top_mod);