From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 Feb 2019 21:26:52 +0000 (+0000)
Subject: whoops, messing up on m_width *sigh*
X-Git-Tag: ls180-24jan2020~1879
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af56c28dd6b44f60eee106d8bd902314676b9381;p=ieee754fpu.git

whoops, messing up on m_width *sigh*
---

diff --git a/src/add/fmul.py b/src/add/fmul.py
index d5c3a830..bb508e1a 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -24,7 +24,7 @@ class FPMUL(FPBase):
         b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
-        mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+        mw = (z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
 
         of = Overflow()
@@ -103,7 +103,7 @@ class FPMUL(FPBase):
 
             #multiply_1
             with m.State("multiply_1"):
-                mw = z.m.m_width
+                mw = z.m_width
                 m.next = "normalise_1"
                 m.d.sync += [
                 z.m.eq(product[mw+3:]),