From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 14 Mar 2019 16:06:56 +0000 (-0700)
Subject: Misspell
X-Git-Tag: yosys-0.9~171^2~59
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af5706c2a38c010e6c7343aeb1c5d6e26a6b7799;p=yosys.git

Misspell
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1978ccf21..f2c3833a4 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -262,7 +262,7 @@ struct SynthXilinxPass : public Pass
 				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
 			}
 
-			Pass::call(design, "shregmap -initt -params -enpol any_or_none");
+			Pass::call(design, "shregmap -init -params -enpol any_or_none");
 			Pass::call(design, "techmap -map +/xilinx/ff_map.v");
 			Pass::call(design, "opt -fast");
 		}