From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 12 Sep 2012 16:07:36 +0000 (+0200)
Subject: examples/de1: fix top
X-Git-Tag: 24jan2021_ls180~2575^2~153
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af64beec53f49c02886635a3f1513ecc79819c80;p=litex.git

examples/de1: fix top
---

diff --git a/examples/de1/top.py b/examples/de1/top.py
index 0f5e39b5..666e3111 100644
--- a/examples/de1/top.py
+++ b/examples/de1/top.py
@@ -20,7 +20,7 @@
 #             & Trig                |
 #                        Arduino (Uart<-->Spi Bridge)
 #                                   |
-#                                De0 Nano
+#                                  De1 
 #                                   |
 #              +--------------------+-----------------------+  
 #            migIo             Signal Generator           migLa
@@ -110,6 +110,7 @@ def get():
 	comb += [
 		led0.eq(control_reg0.field.r[:8])
 	]
+
 	
 	
 	# Dat / Trig Bus
@@ -137,7 +138,7 @@ def get():
 	cst = Constraints(in_clk, in_rst_n, spi2csr0, led0)
 	src_verilog, vns = verilog.convert(frag,
 		cst.get_ios(),
-		name="de0_nano",
+		name="de1",
 		clk_signal = in_clk,
 		rst_signal = in_rst,
 		return_ns=True)