From: Luke Kenneth Casson Leighton Date: Wed, 27 Jun 2018 17:13:10 +0000 (+0100) Subject: add llvm clarification X-Git-Tag: convert-csv-opcode-to-binary~5100 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af65e61911ca0f9b7e44641da51909d6b56e5137;p=libreriscv.git add llvm clarification --- diff --git a/shakti/m_class/libre_3d_gpu.mdwn b/shakti/m_class/libre_3d_gpu.mdwn index 06f6fd2ed..91c9a7fe5 100644 --- a/shakti/m_class/libre_3d_gpu.mdwn +++ b/shakti/m_class/libre_3d_gpu.mdwn @@ -75,7 +75,12 @@ has a *software* (LLVM) renderer: The general aim of this approach is *not* to have the complexity of transferring significant amounts of data structures to and from disparate cores (one Nyuzi, one RISC-V) but to STAY WITHIN THE RISC-V ARCHITECTURE -and simply compile Mesa3D (for RISC-V), gallium3d-llvm (for RISC-V). +and simply compile Mesa3D (for RISC-V), gallium3d-llvm (for RISC-V), +modifying llvm for RISC-V to do the heavy-lifting instead. + +Then it just becomes a matter of adding vector / SIMD / parallelisation +extensions to RISC-V, and adding support in LLVM for the same: + So if considering to base the design on RISC-V, that means turning RISC-V into a vector processor. Now, whilst Hwacha has been located (finally),