From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 6 Mar 2015 09:19:29 +0000 (+0100)
Subject: uart: add phy autodetect function
X-Git-Tag: 24jan2021_ls180~2504
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af66ca7bada73e479cac67dda4966d38ee499ae6;p=litex.git

uart: add phy autodetect function
---

diff --git a/misoclib/com/uart/phy/__init__.py b/misoclib/com/uart/phy/__init__.py
index e69de29b..b9ecab8e 100644
--- a/misoclib/com/uart/phy/__init__.py
+++ b/misoclib/com/uart/phy/__init__.py
@@ -0,0 +1,12 @@
+from misoclib.com.liteeth.common import *
+from misoclib.com.liteeth.generic import *
+
+from misoclib.com.uart.phy.sim import UARTPHYSim
+from misoclib.com.uart.phy.serial import UARTPHYSerial
+
+def UARTPHY(pads, *args, **kwargs):
+	# Autodetect PHY
+	if hasattr(pads, "source_stb"):
+		return UARTPHYSim(pads, *args, **kwargs)
+	else:
+		return UARTPHYSerial(pads, *args, **kwargs)
diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py
index cd42be93..e17f7c5a 100644
--- a/misoclib/soc/__init__.py
+++ b/misoclib/soc/__init__.py
@@ -6,8 +6,7 @@ from migen.fhdl.std import *
 from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 
-from misoclib.com.uart.phy.serial import UARTPHYSerial
-from misoclib.com.uart.phy.sim import UARTPHYSim
+from misoclib.com.uart.phy import UARTPHY
 from misoclib.com import uart
 from misoclib.cpu import CPU, lm32, mor1kx
 from misoclib.cpu.peripherals import identifier, timer
@@ -111,10 +110,7 @@ class SoC(Module):
 			self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
 
 			if with_uart:
-				if getattr(platform, "is_sim", False):
-					self.submodules.uart_phy = UARTPHYSim(platform.request("serial"))
-				else:
-					self.submodules.uart_phy = UARTPHYSerial(platform.request("serial"), clk_freq, uart_baudrate)
+				self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate)
 				self.submodules.uart = uart.UART(self.uart_phy)
 
 			if with_identifier: