From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 28 Jun 2019 08:21:16 +0000 (+0200)
Subject: Improve specify dummy parser, fixes #1144
X-Git-Tag: working-ls180~1225^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af744097496702926f4fbff5d6eb889ad82fa6cf;p=yosys.git

Improve specify dummy parser, fixes #1144

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d89b2dc88..dab5b5919 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1068,11 +1068,18 @@ list_of_path_delay_extra_expressions :
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
 	;
 
+specify_edge_identifier :
+	TOK_POSEDGE | TOK_NEGEDGE ;
+
 parallel_path_description :
-	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
+	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
+	'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
 
 // This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :