From: Curtis Dunham Date: Mon, 21 Sep 2020 14:58:30 +0000 (+0100) Subject: arch-arm: Add ID_MMFR4{,EL1} system registers X-Git-Tag: develop-gem5-snapshot~410 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af80f5f6b919df0bd002f4caf6f7531d535c5c7c;p=gem5.git arch-arm: Add ID_MMFR4{,EL1} system registers Change-Id: Id50ebd2ef2e69ecbd3b7f64a4e9eafe00e283806 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34876 Reviewed-by: Ciro Santilli Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index 0cb973a72..bc5f82378 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -72,6 +72,7 @@ class ArmISA(BaseISA): # SuperSec | Coherent TLB | Bcast Maint | # BP Maint | Cache Maint Set/way | Cache Maint MVA id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3") + id_mmfr4 = Param.UInt32(0x00000000, "Memory Model Feature Register 4") # See section B4.1.84 of ARM ARM # All values are latest for ARMv7-A profile diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc index d2aca9b1d..44becd32d 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc @@ -300,6 +300,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({ { ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" }, { ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" }, { ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" }, + { ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" }, { ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" }, { ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" }, { ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" }, @@ -582,6 +583,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({ { ArmISA::MISCREG_ID_MMFR1_EL1, "ID_MMFR1_EL1" }, { ArmISA::MISCREG_ID_MMFR2_EL1, "ID_MMFR2_EL1" }, { ArmISA::MISCREG_ID_MMFR3_EL1, "ID_MMFR3_EL1" }, + { ArmISA::MISCREG_ID_MMFR4_EL1, "ID_MMFR4_EL1" }, { ArmISA::MISCREG_ID_ISAR0_EL1, "ID_ISAR0_EL1" }, { ArmISA::MISCREG_ID_ISAR1_EL1, "ID_ISAR1_EL1" }, { ArmISA::MISCREG_ID_ISAR2_EL1, "ID_ISAR2_EL1" }, diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index 4d6a95b05..40126cf22 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -365,7 +365,7 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, case MISCREG_ID_MMFR1_EL1: case MISCREG_ID_MMFR2_EL1: case MISCREG_ID_MMFR3_EL1: - //case MISCREG_ID_MMFR4_EL1: + case MISCREG_ID_MMFR4_EL1: case MISCREG_ID_ISAR0_EL1: case MISCREG_ID_ISAR1_EL1: case MISCREG_ID_ISAR2_EL1: diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index dd6a680e6..f4fabc16a 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -350,6 +350,7 @@ ISA::initID32(const ArmISAParams &p) miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1; miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2; miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3; + miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4; miscRegs[MISCREG_ID_ISAR5] = insertBits( miscRegs[MISCREG_ID_ISAR5], 19, 4, @@ -1391,6 +1392,7 @@ ISA::setMiscReg(int misc_reg, RegVal val) case MISCREG_ID_MMFR1: case MISCREG_ID_MMFR2: case MISCREG_ID_MMFR3: + case MISCREG_ID_MMFR4: case MISCREG_ID_ISAR0: case MISCREG_ID_ISAR1: case MISCREG_ID_ISAR2: diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc index a52b5062b..f674c7e58 100644 --- a/src/arch/arm/kvm/arm_cpu.cc +++ b/src/arch/arm/kvm/arm_cpu.cc @@ -157,6 +157,7 @@ static uint64_t invariant_reg_vector[] = { REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3 REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4 REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5 + REG_CP32(15, 0, 0, 2, 6), // ID_MMFR4 REG_CP32(15, 0, 0, 2, 7), // ID_ISAR6 REG_CP32(15, 0, 1, 0, 0), // CSSIDR diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 825811fd1..b5af9b659 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -394,7 +394,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) case 5: return MISCREG_ID_ISAR5; case 6: - return MISCREG_RAZ; // read as zero + return MISCREG_ID_MMFR4; case 7: return MISCREG_ID_ISAR6; } @@ -2070,6 +2070,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_ID_ISAR4_EL1; case 5: return MISCREG_ID_ISAR5_EL1; + case 6: + return MISCREG_ID_MMFR4_EL1; case 7: return MISCREG_ID_ISAR6_EL1; } @@ -3780,6 +3782,8 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_MMFR3) .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ID_MMFR4) + .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR0) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_ISAR1) @@ -4705,6 +4709,9 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_ID_MMFR3_EL1) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_ID_MMFR3); + InitReg(MISCREG_ID_MMFR4_EL1) + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_MMFR4); InitReg(MISCREG_ID_ISAR0_EL1) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_ID_ISAR0); diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 26ca9b1de..a2adef4c1 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -212,6 +212,7 @@ namespace ArmISA MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, + MISCREG_ID_MMFR4, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, @@ -542,6 +543,7 @@ namespace ArmISA MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1, MISCREG_ID_MMFR3_EL1, + MISCREG_ID_MMFR4_EL1, MISCREG_ID_ISAR0_EL1, MISCREG_ID_ISAR1_EL1, MISCREG_ID_ISAR2_EL1, @@ -1321,6 +1323,7 @@ namespace ArmISA "id_mmfr1", "id_mmfr2", "id_mmfr3", + "id_mmfr4", "id_isar0", "id_isar1", "id_isar2", @@ -1649,6 +1652,7 @@ namespace ArmISA "id_mmfr1_el1", "id_mmfr2_el1", "id_mmfr3_el1", + "id_mmfr4_el1", "id_isar0_el1", "id_isar1_el1", "id_isar2_el1", diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index 6131d2c86..cdb24cac0 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -200,6 +200,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { { "id_mmfr1", MISCREG_ID_MMFR1 }, { "id_mmfr2", MISCREG_ID_MMFR2 }, { "id_mmfr3", MISCREG_ID_MMFR3 }, + { "id_mmfr4", MISCREG_ID_MMFR4 }, { "id_isar0", MISCREG_ID_ISAR0 }, { "id_isar1", MISCREG_ID_ISAR1 }, { "id_isar2", MISCREG_ID_ISAR2 }, @@ -499,6 +500,7 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = { { "id_mmfr1_el1", MISCREG_ID_MMFR1_EL1 }, { "id_mmfr2_el1", MISCREG_ID_MMFR2_EL1 }, { "id_mmfr3_el1", MISCREG_ID_MMFR3_EL1 }, + { "id_mmfr4_el1", MISCREG_ID_MMFR4_EL1 }, { "id_isar0_el1", MISCREG_ID_ISAR0_EL1 }, { "id_isar1_el1", MISCREG_ID_ISAR1_EL1 }, { "id_isar2_el1", MISCREG_ID_ISAR2_EL1 }, diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 43e474df9..93e0a78fa 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -659,6 +659,7 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, case MISCREG_ID_MMFR1: case MISCREG_ID_MMFR2: case MISCREG_ID_MMFR3: + case MISCREG_ID_MMFR4: case MISCREG_ID_ISAR0: case MISCREG_ID_ISAR1: case MISCREG_ID_ISAR2: