From: Giacomo Travaglini Date: Wed, 30 Sep 2020 13:49:11 +0000 (+0100) Subject: fastmodel: Add IrisMMU model X-Git-Tag: develop-gem5-snapshot~678 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af8794c378efc519716b98515342d00fc1267cee;p=gem5.git fastmodel: Add IrisMMU model JIRA: https://gem5.atlassian.net/browse/GEM5-790 Change-Id: Ida4ec76df5f6192e34a5b3fc6d002c473d48b387 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35415 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py index a73e46ea3..20699fad4 100644 --- a/src/arch/arm/fastmodel/iris/Iris.py +++ b/src/arch/arm/fastmodel/iris/Iris.py @@ -1,3 +1,15 @@ +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright 2019 Google, Inc. # # Redistribution and use in source and binary forms, with or without @@ -30,12 +42,20 @@ from m5.objects.BaseCPU import BaseCPU from m5.objects.BaseInterrupts import BaseInterrupts from m5.objects.BaseISA import BaseISA from m5.objects.BaseTLB import BaseTLB +from m5.objects.BaseMMU import BaseMMU class IrisTLB(BaseTLB): type = 'IrisTLB' cxx_class = 'Iris::TLB' cxx_header = 'arch/arm/fastmodel/iris/tlb.hh' +class IrisMMU(BaseMMU): + type = 'IrisMMU' + cxx_class = 'Iris::MMU' + cxx_header = 'arch/arm/fastmodel/iris/mmu.hh' + itb = IrisTLB() + dtb = IrisTLB() + class IrisInterrupts(BaseInterrupts): type = 'IrisInterrupts' cxx_class = 'Iris::Interrupts' diff --git a/src/arch/arm/fastmodel/iris/SConscript b/src/arch/arm/fastmodel/iris/SConscript index 9586f0fca..2e0b52b88 100644 --- a/src/arch/arm/fastmodel/iris/SConscript +++ b/src/arch/arm/fastmodel/iris/SConscript @@ -32,6 +32,7 @@ SimObject('Iris.py') Source('cpu.cc') Source('interrupts.cc') Source('isa.cc') +Source('mmu.cc') Source('tlb.cc') Source('thread_context.cc') diff --git a/src/arch/arm/fastmodel/iris/mmu.cc b/src/arch/arm/fastmodel/iris/mmu.cc new file mode 100644 index 000000000..407c18a90 --- /dev/null +++ b/src/arch/arm/fastmodel/iris/mmu.cc @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/arm/fastmodel/iris/mmu.hh" + +Iris::MMU * +IrisMMUParams::create() +{ + return new Iris::MMU(this); +} diff --git a/src/arch/arm/fastmodel/iris/mmu.hh b/src/arch/arm/fastmodel/iris/mmu.hh new file mode 100644 index 000000000..19899511d --- /dev/null +++ b/src/arch/arm/fastmodel/iris/mmu.hh @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__ +#define __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__ + +#include "arch/generic/mmu.hh" + +#include "params/IrisMMU.hh" + +namespace Iris +{ + +class MMU : public BaseMMU +{ + public: + MMU(const Params *p) : BaseMMU(p) {} +}; + +} // namespace Iris + +#endif // __ARCH_ARM_FASTMODEL_IRIS_MMU_HH__