From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Jun 2019 10:17:45 +0000 (+0100)
Subject: add map table
X-Git-Tag: convert-csv-opcode-to-binary~4455
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af93338868cae386d30b99d51b4d478afe1e54df;p=libreriscv.git

add map table
---

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 3c7caf337..2df25f0cf 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -512,10 +512,18 @@ Standard RV32/RV64 executables.
 | ------ | | -   | ------ | ------- |
 | 0      | | i/f | vew0   | regnum  |
 
+Showing the mapping (relationship) between 8-bit and 16-bit format:
+
+| RegCAM | 15      | (14..8)    | 7   | (6..5) | (4..0)  |
+| ------ | -       | -          | -   | ------ | ------- |
+| 0      | isvec=1 | regnum0<<2 | i/f | vew0   | regnum0 |
+| 1      | isvec=1 | regnum1<<2 | i/f | vew1   | regnum1 |
+| 2      | isvec=1 | regnum2<<2 | i/f | vew2   | regnum2 |
+| 3      | isvec=1 | regnum2<<2 | i/f | vew3   | regnum3 |
+
 i/f is set to "1" to indicate that the redirection/tag entry is to
 be applied to integer registers; 0 indicates that it is relevant to
-floating-point
-registers.
+floating-point registers.
 
 The 8 bit format is used for a much more compact expression. "isvec"
 is implicit and, similar to [[sv-prefix-proposal]], the target vector