From: lkcl <lkcl@web>
Date: Sun, 4 Jun 2023 11:30:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=af9b7a0ca94afcbe1ab129b5c37f84c15cacebc7;p=libreriscv.git

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diff --git a/openpower/sv/ls010/trial_addi.mdwn b/openpower/sv/ls010/trial_addi.mdwn
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+# Example demonstration instruction modified to SVP64 (better)
+
+<!-- hide -->
+Background: <https://bugs.libre-soc.org/show_bug.cgi?id=1056#c56>
+<!-- show -->
+
+**Add Immediate** D-Form
+
+* addi RT,RA,SI
+
+```
+    DWI:
+        |    14 |   RT            |    RA       |     SI       |
+        | 0     | 6               | 11          | 16        31 |
+```
+
+**Prefixed Add Immediate** MLS:D-form
+
+* paddi RT,RA,SI,R
+
+```
+    Prefix:
+        |    1  |   2    | 0 | // | R  | //  |     si0         |
+        | 0     | 6      | 8 | 9  | 11 | 12  | 14           31 |
+
+    Suffix::
+        |    14 |   RT            |    RA       | si1          |
+        | 0     | 6               | 11          | 16        31 |
+```
+
+**Vectorized Add Immediate** SVP64-RM-1S1D/EXTRA3/Normal:D-form
+
+* sv.addi RT,RA,SI 
+
+```
+    Prefix: :
+        |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
+        | 0     | 6      | 8         | 17    26 | 27        31 |
+    Suffix:
+        |    14 |   RT            |    RA       |     SI       |
+        | 0     | 6               | 11          | 16        31 |
+```
+
+Pseudo-code:
+
+```
+    if "addi" then
+        RT <- (RA|0) + EXTS64(SI)
+    if "paddi" & R=0 then
+        RT <- (RA|0) + EXTS64(si0||si1)
+    if "paddi" & R=1 then
+        RT <- CIA + EXTS64(si0||si1)
+
+```
+
+Special Registers Altered:
+
+    None
+