From: lkcl <lkcl@web>
Date: Thu, 2 Sep 2021 12:27:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~257
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afa0352222f267f6c0942b2f093937cc614f1969;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index d4487dba9..9d3b4cdd3 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -129,6 +129,8 @@ Fields:
 * **ALL** when set, all branch conditional tests must pass in order for
   the branch to succeed. When clear, it is the first sequentially
   encountered successful test that causes the branch to succeed.
+  This is identical behaviour to how programming languages perform
+  early-exit on Boolean Logic chains.
 * **VLI** VLSET is identical to Data-dependent Fail-First mode.
   In VLSET mode, VL is set equal (truncated) to the first point
   where, assuming Conditions are tested sequentially, the branch succeeds