From: Glenn Kennard Date: Fri, 15 Aug 2014 08:30:58 +0000 (+0200) Subject: r600g: Implement ARB_derivative_control X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afa7df9b78c0e7b14d2069faa8bc83aa2548b8e5;p=mesa.git r600g: Implement ARB_derivative_control Requires Evergreen/Cayman marek: update release notes Signed-off-by: Glenn Kennard Signed-off-by: Marek Olšák --- diff --git a/docs/GL3.txt b/docs/GL3.txt index 12b8f62283c..b38e42c19dc 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -188,7 +188,7 @@ GL 4.5, GLSL 4.50: GL_ARB_clip_control not started GL_ARB_conditional_render_inverted not started GL_ARB_cull_distance not started - GL_ARB_derivative_control DONE (i965, nv50, nvc0) + GL_ARB_derivative_control DONE (i965, nv50, nvc0, r600) GL_ARB_direct_state_access not started GL_ARB_get_texture_sub_image started (Brian Paul) GL_ARB_shader_texture_image_samples not started diff --git a/docs/relnotes/10.3.html b/docs/relnotes/10.3.html index 0f22d70ae71..1afa93294f9 100644 --- a/docs/relnotes/10.3.html +++ b/docs/relnotes/10.3.html @@ -47,7 +47,7 @@ Note: some of the new features are only available with certain drivers.
  • GL_ARB_ES3_compatibility on nv50, nvc0, r600, radeonsi, softpipe, llvmpipe
  • GL_ARB_clear_texture on i965
  • GL_ARB_compressed_texture_pixel_storage on all drivers
    • -
  • GL_ARB_derivative_control on i965, nv50, nvc0
    • +
  • GL_ARB_derivative_control on i965, nv50, nvc0, r600
  • GL_ARB_draw_indirect on nvc0, radeonsi
  • GL_ARB_explicit_uniform_location (all drivers that support GLSL)
  • GL_ARB_fragment_layer_viewport on nv50, nvc0, llvmpipe, r600
    • diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 8a5ba7951bb..bf52a192c9c 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -305,6 +305,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_TEXTURE_QUERY_LOD: + case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: return family >= CHIP_CEDAR ? 1 : 0; case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: return family >= CHIP_CEDAR ? 4 : 0; @@ -319,7 +320,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_DRAW_INDIRECT: - case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: return 0; /* Stream output. */ diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 481e9eb29b1..3f089b4f7d9 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -5319,6 +5319,11 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) tex.src_gpr = src_gpr; tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index; + if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE || + inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) { + tex.inst_mod = 1; /* per pixel gradient calculation instead of per 2x2 quad */ + } + if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) { int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX]; tex.inst_mod = texture_component_select; @@ -6789,9 +6794,8 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = { {76, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else}, {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif}, - /* gap */ - {79, 0, ALU_OP0_NOP, tgsi_unsupported}, - {80, 0, ALU_OP0_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DDX_FINE, 0, ALU_OP0_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DDY_FINE, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2}, @@ -6992,9 +6996,8 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { {76, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else}, {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif}, - /* gap */ - {79, 0, ALU_OP0_NOP, tgsi_unsupported}, - {80, 0, ALU_OP0_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DDX_FINE, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex}, + {TGSI_OPCODE_DDY_FINE, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex}, {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2}, @@ -7195,9 +7198,8 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = { {76, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_ELSE, 0, ALU_OP0_NOP, tgsi_else}, {TGSI_OPCODE_ENDIF, 0, ALU_OP0_NOP, tgsi_endif}, - /* gap */ - {79, 0, ALU_OP0_NOP, tgsi_unsupported}, - {80, 0, ALU_OP0_NOP, tgsi_unsupported}, + {TGSI_OPCODE_DDX_FINE, 0, FETCH_OP_GET_GRADIENTS_H, tgsi_tex}, + {TGSI_OPCODE_DDY_FINE, 0, FETCH_OP_GET_GRADIENTS_V, tgsi_tex}, {TGSI_OPCODE_PUSHA, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_POPA, 0, ALU_OP0_NOP, tgsi_unsupported}, {TGSI_OPCODE_CEIL, 0, ALU_OP1_CEIL, tgsi_op2},