From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 13 Jul 2020 13:55:04 +0000 (+0100)
Subject: document rb as sh
X-Git-Tag: div_pipeline~60
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afb3fa284ae21fccb6ee649ae6b7ef7ab41e3e68;p=soc.git

document rb as sh
---

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 21f8f5bc..0ab4c460 100644
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -32,6 +32,10 @@ class ShiftRotMainStage(PipeModBase):
         op = self.i.ctx.op
         o = self.o.o
 
+        # NOTE: the sh field immediate is read in by PowerDecode2
+        # (actually DecodeRB), whereupon by way of rb "immediate" mode
+        # it ends up in self.i.rb.
+
         # obtain me and mb fields from instruction.
         m_fields = self.fields.instrs['M']
         md_fields = self.fields.instrs['MD']
@@ -50,7 +54,7 @@ class ShiftRotMainStage(PipeModBase):
             rotator.mb_extra.eq(mb_extra),
             rotator.rs.eq(self.i.rs),
             rotator.ra.eq(self.i.a),
-            rotator.shift.eq(self.i.rb),
+            rotator.shift.eq(self.i.rb), # can also be sh (in immediate mode)
             rotator.is_32bit.eq(op.is_32bit),
             rotator.arith.eq(op.is_signed),
         ]