From: colepoirier <colepoirier@gmail.com>
Date: Wed, 3 Jun 2020 00:07:39 +0000 (-0700)
Subject: Attempted to fix OP_RFID in TRAP pipeline
X-Git-Tag: div_pipeline~637^2~24
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afbc6cf35bbd3c4f051d6d0e45860d9fa730ad46;p=soc.git

Attempted to fix OP_RFID in TRAP pipeline
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 03e5c2e4..d165aefb 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -163,8 +163,12 @@ class TrapMainStage(PipeModBase):
                     ctrl_tmp.msr(MSR_DR) <= '1';
                 end if;
                 """
-                comb += self.o.msr.data.eq(Cat(b[63:31], b[26:22], b[15:0]))
-                comb += self.o.msr.ok.eq(a)
+                comb += self.o.msr.data[:16].eq(b[:16])
+                comb += self.o.msr.data[22:27].eq(b[22:27])
+                comb += self.o.msr.data[31:]
+                comb += self.o.msr.ok.eq(1)
+                comb += self.o.msr.data.eq(b)
+                comb += self.o.msr.ok.eq(1)
 
             # TODO
             with m.Case(InternalOp.OP_SC):