From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Apr 2019 13:33:31 +0000 (+0100)
Subject: test trigger=1 in test 13
X-Git-Tag: ls180-24jan2020~1298
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afc52ecdc28573ed37137c52ff978c53ebaefe6e;p=ieee754fpu.git

test trigger=1 in test 13
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 2f545428..23589ef3 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -701,7 +701,7 @@ class BufferedPipeline2(ControlBase):
 
         # previous valid and ready
         with self.m.If(p_i_valid_p_o_ready):
-                self.m.d.sync += [self.n.o_valid.eq(1),      # output valid
+            self.m.d.sync += [self.n.o_valid.eq(1),      # output valid
                                   eq(self.n.o_data, result), # update output
                                  ]
         # previous invalid or not ready, however next is accepting
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 9fec02a7..df63978c 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -654,14 +654,14 @@ def test12_resultfn(o_data, expected, i, o):
 # Test 13
 ######################################################################
 
-class ExampleUnBufDelayedPipe(BufferedPipeline):
+class ExampleUnBufDelayedPipe(BufferedPipeline2):
 
     def __init__(self):
-        stage = ExampleStageDelayCls()
-        BufferedPipeline.__init__(self, stage, stage_ctl=True)
+        stage = ExampleStageDelayCls(valid_trigger=1)
+        BufferedPipeline2.__init__(self, stage, stage_ctl=True)
 
     def elaborate(self, platform):
-        m = BufferedPipeline.elaborate(self, platform)
+        m = BufferedPipeline2.elaborate(self, platform)
         m.submodules.stage = self.stage
         return m