From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 Mar 2019 13:20:20 +0000 (+0000)
Subject: whitespace cleanup
X-Git-Tag: ls180-24jan2020~1469
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afe9d6d08cf88ebeb0395d465176e88408c97a48;p=ieee754fpu.git

whitespace cleanup
---

diff --git a/src/add/test_prioritymux_pipe.py b/src/add/test_prioritymux_pipe.py
index 6b41f1b4..d2167366 100644
--- a/src/add/test_prioritymux_pipe.py
+++ b/src/add/test_prioritymux_pipe.py
@@ -7,7 +7,6 @@ from nmigen.cli import verilog, rtlil
 from multipipe import CombMultiInPipeline, InputPriorityArbiter
 
 
-
 class PriorityUnbufferedPipeline(CombMultiInPipeline):
     def __init__(self, stage, p_len=4):
         p_mux = InputPriorityArbiter(self, p_len)
@@ -17,6 +16,7 @@ class PriorityUnbufferedPipeline(CombMultiInPipeline):
         return self.p_mux.ports()
         #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
 
+
 class PassData:
     def __init__(self):
         self.mid = Signal(2, reset_less=True)