From: Jacob Lifshay Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700) Subject: split out instructions from openpower/isa/system.mdwn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aff782105c86c1aae4807d7e5577c3c8c37a70f1;p=openpower-isa.git split out instructions from openpower/isa/system.mdwn --- diff --git a/openpower/isa/system.mdwn b/openpower/isa/system.mdwn index 74f06c50..7d3dab1d 100644 --- a/openpower/isa/system.mdwn +++ b/openpower/isa/system.mdwn @@ -4,124 +4,12 @@ -# System Call +[[!inline pagenames="openpower/isa/system/sc" raw="yes"]] -SC-Form +[[!inline pagenames="openpower/isa/system/scv" raw="yes"]] -* sc LEV +[[!inline pagenames="openpower/isa/system/rfscv" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/system/rfid" raw="yes"]] - SRR0 <-iea CIA + 4 - SRR1[33:36] <- 0 - SRR1[42:47] <- 0 - SRR1[0:32] <- MSR[0:32] - SRR1[37:41] <- MSR[37:41] - SRR1[48:63] <- MSR[48:63] - MSR <- new_value - NIA <- 0x0000_0000_0000_0C00 - -Special Registers Altered: - - SRR0 SRR1 MSR - -# System Call Vectored - -SC-Form - -* scv LEV - -Pseudo-code: - - LR <- CIA + 4 - SRR1[33:36] <- undefined([0]*4) - SRR1[42:47] <- undefined([0]*6) - SRR1[0:32] <- MSR[0:32] - SRR1[37:41] <- MSR[37:41] - SRR1[48:63] <- MSR[48:63] - MSR <- new_value - NIA <- vectored - -Special Registers Altered: - - LR CTR MSR - -# Return From System Call Vectored - -XL-Form - -* rfscv - -Pseudo-code: - - if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then - MSR[29:31] <- CTR[29:31] - MSR[48] <- CTR[49] - MSR[58] <- CTR[49] - MSR[59] <- CTR[49] - MSR[0:2] <- CTR[0:2] - MSR[4:28] <- CTR[4:28] - MSR[32] <- CTR[32] - MSR[37:41] <- CTR[37:41] - MSR[49:50] <- CTR[49:50] - MSR[52:57] <- CTR[52:57] - MSR[60:63] <- CTR[60:63] - NIA <-iea LR[0:61] || 0b00 - -Special Registers Altered: - - MSR - -# Return From Interrupt Doubleword - -XL-Form - -* rfid - -Pseudo-code: - - MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51])) - MSR[3] <- (MSR[3] & SRR1[3]) - if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then - MSR[29:31] <- SRR1[29:31] - MSR[48] <- SRR1[48] | SRR1[49] - MSR[58] <- SRR1[58] | SRR1[49] - MSR[59] <- SRR1[59] | SRR1[49] - MSR[0:2] <- SRR1[0:2] - MSR[4:28] <- SRR1[4:28] - MSR[32] <- SRR1[32] - MSR[37:41] <- SRR1[37:41] - MSR[49:50] <- SRR1[49:50] - MSR[52:57] <- SRR1[52:57] - MSR[60:63] <- SRR1[60:63] - NIA <-iea SRR0[0:61] || 0b00 - -Special Registers Altered: - - MSR - -# Hypervisor Return From Interrupt Doubleword - -XL-Form - -* hrfid - -Pseudo-code: - - if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then - MSR[29:31] <- HSRR1[29:31] - MSR[48] <- HSRR1[48] | HSRR1[49] - MSR[58] <- HSRR1[58] | HSRR1[49] - MSR[59] <- HSRR1[59] | HSRR1[49] - MSR[0:28] <- HSRR1[0:28] - MSR[32] <- HSRR1[32] - MSR[37:41] <- HSRR1[37:41] - MSR[49:57] <- HSRR1[49:57] - MSR[60:63] <- HSRR1[60:63] - NIA <-iea HSRR0[0:61] || 0b00 - -Special Registers Altered: - - MSR - - +[[!inline pagenames="openpower/isa/system/hrfid" raw="yes"]] diff --git a/openpower/isa/system/hrfid.mdwn b/openpower/isa/system/hrfid.mdwn new file mode 100644 index 00000000..46167431 --- /dev/null +++ b/openpower/isa/system/hrfid.mdwn @@ -0,0 +1,15 @@ +# Hypervisor Return From Interrupt Doubleword + +XL-Form + +* hrfid + +Pseudo-code: + +[[!inline pagenames="openpower/isa/system/hrfid_code" raw="yes"]] + +Special Registers Altered: + + MSR + + diff --git a/openpower/isa/system/hrfid_code.mdwn b/openpower/isa/system/hrfid_code.mdwn new file mode 100644 index 00000000..4fe186d4 --- /dev/null +++ b/openpower/isa/system/hrfid_code.mdwn @@ -0,0 +1,11 @@ + if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then + MSR[29:31] <- HSRR1[29:31] + MSR[48] <- HSRR1[48] | HSRR1[49] + MSR[58] <- HSRR1[58] | HSRR1[49] + MSR[59] <- HSRR1[59] | HSRR1[49] + MSR[0:28] <- HSRR1[0:28] + MSR[32] <- HSRR1[32] + MSR[37:41] <- HSRR1[37:41] + MSR[49:57] <- HSRR1[49:57] + MSR[60:63] <- HSRR1[60:63] + NIA <-iea HSRR0[0:61] || 0b00 diff --git a/openpower/isa/system/rfid.mdwn b/openpower/isa/system/rfid.mdwn new file mode 100644 index 00000000..73775093 --- /dev/null +++ b/openpower/isa/system/rfid.mdwn @@ -0,0 +1,13 @@ +# Return From Interrupt Doubleword + +XL-Form + +* rfid + +Pseudo-code: + +[[!inline pagenames="openpower/isa/system/rfid_code" raw="yes"]] + +Special Registers Altered: + + MSR diff --git a/openpower/isa/system/rfid_code.mdwn b/openpower/isa/system/rfid_code.mdwn new file mode 100644 index 00000000..ec2c7969 --- /dev/null +++ b/openpower/isa/system/rfid_code.mdwn @@ -0,0 +1,15 @@ + MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51])) + MSR[3] <- (MSR[3] & SRR1[3]) + if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then + MSR[29:31] <- SRR1[29:31] + MSR[48] <- SRR1[48] | SRR1[49] + MSR[58] <- SRR1[58] | SRR1[49] + MSR[59] <- SRR1[59] | SRR1[49] + MSR[0:2] <- SRR1[0:2] + MSR[4:28] <- SRR1[4:28] + MSR[32] <- SRR1[32] + MSR[37:41] <- SRR1[37:41] + MSR[49:50] <- SRR1[49:50] + MSR[52:57] <- SRR1[52:57] + MSR[60:63] <- SRR1[60:63] + NIA <-iea SRR0[0:61] || 0b00 diff --git a/openpower/isa/system/rfscv.mdwn b/openpower/isa/system/rfscv.mdwn new file mode 100644 index 00000000..d9776331 --- /dev/null +++ b/openpower/isa/system/rfscv.mdwn @@ -0,0 +1,13 @@ +# Return From System Call Vectored + +XL-Form + +* rfscv + +Pseudo-code: + +[[!inline pagenames="openpower/isa/system/rfscv_code" raw="yes"]] + +Special Registers Altered: + + MSR diff --git a/openpower/isa/system/rfscv_code.mdwn b/openpower/isa/system/rfscv_code.mdwn new file mode 100644 index 00000000..c316f0c0 --- /dev/null +++ b/openpower/isa/system/rfscv_code.mdwn @@ -0,0 +1,13 @@ + if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then + MSR[29:31] <- CTR[29:31] + MSR[48] <- CTR[49] + MSR[58] <- CTR[49] + MSR[59] <- CTR[49] + MSR[0:2] <- CTR[0:2] + MSR[4:28] <- CTR[4:28] + MSR[32] <- CTR[32] + MSR[37:41] <- CTR[37:41] + MSR[49:50] <- CTR[49:50] + MSR[52:57] <- CTR[52:57] + MSR[60:63] <- CTR[60:63] + NIA <-iea LR[0:61] || 0b00 diff --git a/openpower/isa/system/sc.mdwn b/openpower/isa/system/sc.mdwn new file mode 100644 index 00000000..0a3f0366 --- /dev/null +++ b/openpower/isa/system/sc.mdwn @@ -0,0 +1,13 @@ +# System Call + +SC-Form + +* sc LEV + +Pseudo-code: + +[[!inline pagenames="openpower/isa/system/sc_code" raw="yes"]] + +Special Registers Altered: + + SRR0 SRR1 MSR diff --git a/openpower/isa/system/sc_code.mdwn b/openpower/isa/system/sc_code.mdwn new file mode 100644 index 00000000..256f18c7 --- /dev/null +++ b/openpower/isa/system/sc_code.mdwn @@ -0,0 +1,8 @@ + SRR0 <-iea CIA + 4 + SRR1[33:36] <- 0 + SRR1[42:47] <- 0 + SRR1[0:32] <- MSR[0:32] + SRR1[37:41] <- MSR[37:41] + SRR1[48:63] <- MSR[48:63] + MSR <- new_value + NIA <- 0x0000_0000_0000_0C00 diff --git a/openpower/isa/system/scv.mdwn b/openpower/isa/system/scv.mdwn new file mode 100644 index 00000000..8de1e9af --- /dev/null +++ b/openpower/isa/system/scv.mdwn @@ -0,0 +1,13 @@ +# System Call Vectored + +SC-Form + +* scv LEV + +Pseudo-code: + +[[!inline pagenames="openpower/isa/system/scv_code" raw="yes"]] + +Special Registers Altered: + + LR CTR MSR diff --git a/openpower/isa/system/scv_code.mdwn b/openpower/isa/system/scv_code.mdwn new file mode 100644 index 00000000..0e042f42 --- /dev/null +++ b/openpower/isa/system/scv_code.mdwn @@ -0,0 +1,8 @@ + LR <- CIA + 4 + SRR1[33:36] <- undefined([0]*4) + SRR1[42:47] <- undefined([0]*6) + SRR1[0:32] <- MSR[0:32] + SRR1[37:41] <- MSR[37:41] + SRR1[48:63] <- MSR[48:63] + MSR <- new_value + NIA <- vectored