From: Jan Hubicka <jh@suse.cz>
Date: Tue, 4 Feb 2003 20:43:04 +0000 (+0100)
Subject: i386-cadd.c: Compile using -march=k8.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=afffc4e236385f27690bf10f6acec2ec92557305;p=gcc.git

i386-cadd.c: Compile using -march=k8.

	* gcc.dg/i386-cadd.c:  Compile using -march=k8.
	* gcc.dg/i386-cmov?.c:  Likewise.
	* gcc.dg/i386-fpcvt-?.c:  Likewise.
	* gcc.dg/i386-ssefp-1.c:  Likewise.
	* gcc.dg/i386-ssetype-?.c:  Likewise; fix for register passing
	convetions.

From-SVN: r62394
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6ed5733aa21..1d32a755acd 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+Tue Feb  4 21:41:09 CET 2003  Jan Hubicka  <jh@suse.cz>
+
+	* gcc.dg/i386-cadd.c:  Compile using -march=k8.
+	* gcc.dg/i386-cmov?.c:  Likewise.
+	* gcc.dg/i386-fpcvt-?.c:  Likewise.
+	* gcc.dg/i386-ssefp-1.c:  Likewise.
+	* gcc.dg/i386-ssetype-?.c:  Likewise; fix for register passing
+	convetions.
+
 2003-02-03  Mark Mitchell  <mark@codesourcery.com>
 
 	PR c++/7129
diff --git a/gcc/testsuite/gcc.dg/i386-cadd.c b/gcc/testsuite/gcc.dg/i386-cadd.c
index 46bfd221e07..ef6c16bee78 100644
--- a/gcc/testsuite/gcc.dg/i386-cadd.c
+++ b/gcc/testsuite/gcc.dg/i386-cadd.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sbb" } } */
 
 /* Conditional increment is best done using sbb $-1, val.  */
diff --git a/gcc/testsuite/gcc.dg/i386-cmov1.c b/gcc/testsuite/gcc.dg/i386-cmov1.c
index 1f7ff727bc4..38aa6a62a60 100644
--- a/gcc/testsuite/gcc.dg/i386-cmov1.c
+++ b/gcc/testsuite/gcc.dg/i386-cmov1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sar.*magic_namea" } } */
 /* { dg-final { scan-assembler "sar.*magic_nameb" } } */
 /* { dg-final { scan-assembler "sar.*magic_namec" } } */
diff --git a/gcc/testsuite/gcc.dg/i386-cmov2.c b/gcc/testsuite/gcc.dg/i386-cmov2.c
index f4edfbf64c0..cd6457f0d5f 100644
--- a/gcc/testsuite/gcc.dg/i386-cmov2.c
+++ b/gcc/testsuite/gcc.dg/i386-cmov2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sbb" } } */
 
 /* This conditional move is fastest to be done using sbb.  */
diff --git a/gcc/testsuite/gcc.dg/i386-cmov3.c b/gcc/testsuite/gcc.dg/i386-cmov3.c
index 9e5a6361e52..6ef2675297d 100644
--- a/gcc/testsuite/gcc.dg/i386-cmov3.c
+++ b/gcc/testsuite/gcc.dg/i386-cmov3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "cmov" } } */
 
 /* This conditional move is fastest to be done using cmov.  */
diff --git a/gcc/testsuite/gcc.dg/i386-cmov4.c b/gcc/testsuite/gcc.dg/i386-cmov4.c
index 1601f2251b5..e293b34abc1 100644
--- a/gcc/testsuite/gcc.dg/i386-cmov4.c
+++ b/gcc/testsuite/gcc.dg/i386-cmov4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "cmov" } } */
 
 /* Verify that if conversion happends for memory references.  */
diff --git a/gcc/testsuite/gcc.dg/i386-cmov5.c b/gcc/testsuite/gcc.dg/i386-cmov5.c
index d119abd4160..112a9933bbc 100644
--- a/gcc/testsuite/gcc.dg/i386-cmov5.c
+++ b/gcc/testsuite/gcc.dg/i386-cmov5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -march=athlon" } */
+/* { dg-options "-O2 -march=k8" } */
 /* { dg-final { scan-assembler "sbb" } } */
 
 int
diff --git a/gcc/testsuite/gcc.dg/i386-fpcvt-1.c b/gcc/testsuite/gcc.dg/i386-fpcvt-1.c
index 716073eeeb3..6e65b104163 100644
--- a/gcc/testsuite/gcc.dg/i386-fpcvt-1.c
+++ b/gcc/testsuite/gcc.dg/i386-fpcvt-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler-not "cvtss2sd" } } */
 float a,b;
 main()
diff --git a/gcc/testsuite/gcc.dg/i386-fpcvt-2.c b/gcc/testsuite/gcc.dg/i386-fpcvt-2.c
index 12d149b1399..613c2076019 100644
--- a/gcc/testsuite/gcc.dg/i386-fpcvt-2.c
+++ b/gcc/testsuite/gcc.dg/i386-fpcvt-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler-not "cvtss2sd" } } */
 float a,b;
 main()
diff --git a/gcc/testsuite/gcc.dg/i386-fpcvt-3.c b/gcc/testsuite/gcc.dg/i386-fpcvt-3.c
index 9a7733363ba..69d7e3d2cd6 100644
--- a/gcc/testsuite/gcc.dg/i386-fpcvt-3.c
+++ b/gcc/testsuite/gcc.dg/i386-fpcvt-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler-not "cvtss2sd" } } */
 float a,b;
 main()
diff --git a/gcc/testsuite/gcc.dg/i386-mmx-3.c b/gcc/testsuite/gcc.dg/i386-mmx-3.c
index f44fa0fbfdd..b417ddae9ba 100644
--- a/gcc/testsuite/gcc.dg/i386-mmx-3.c
+++ b/gcc/testsuite/gcc.dg/i386-mmx-3.c
@@ -1,7 +1,7 @@
 /* PR target/8870 */
 /* Originator: otaylor@redhat.com */
-/* { dg-do compile { target i?86-*-* } } */
-/* { dg-options "-O1 -mmmx -march=i686" } */
+/* { dg-do compile { target i?86-*-* x86_64-*-*} } */
+/* { dg-options "-O1 -mmmx -march=k8" } */
 
 typedef int v4hi __attribute__ ((mode (V4HI)));
 
diff --git a/gcc/testsuite/gcc.dg/i386-ssefp-1.c b/gcc/testsuite/gcc.dg/i386-ssefp-1.c
index ad6f109bc99..d11a72f1118 100644
--- a/gcc/testsuite/gcc.dg/i386-ssefp-1.c
+++ b/gcc/testsuite/gcc.dg/i386-ssefp-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon -mfpmath=sse" } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
 /* { dg-final { scan-assembler "maxsd" } } */
 /* { dg-final { scan-assembler "minsd" } } */
 double x;
diff --git a/gcc/testsuite/gcc.dg/i386-ssefp-2.c b/gcc/testsuite/gcc.dg/i386-ssefp-2.c
index 0d1ced2fee0..68790241678 100644
--- a/gcc/testsuite/gcc.dg/i386-ssefp-2.c
+++ b/gcc/testsuite/gcc.dg/i386-ssefp-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon -mfpmath=sse" } */
+/* { dg-options "-O2 -msse2 -march=k8 -mfpmath=sse" } */
 /* { dg-final { scan-assembler "maxsd" } } */
 /* { dg-final { scan-assembler "minsd" } } */
 double x;
diff --git a/gcc/testsuite/gcc.dg/i386-ssetype-1.c b/gcc/testsuite/gcc.dg/i386-ssetype-1.c
index 6953b751b43..87921713bec 100644
--- a/gcc/testsuite/gcc.dg/i386-ssetype-1.c
+++ b/gcc/testsuite/gcc.dg/i386-ssetype-1.c
@@ -1,32 +1,35 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
-/* { dg-final { scan-assembler "andpd.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "andnpd.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "xorpd.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "orpd.*\[bs\]p" } } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andpd.*magic" } } */
+/* { dg-final { scan-assembler "andnpd.*magic" } } */
+/* { dg-final { scan-assembler "xorpd.*magic" } } */
+/* { dg-final { scan-assembler "orpd.*magic" } } */
 /* { dg-final { scan-assembler-not "movdqa" } } */
-/* { dg-final { scan-assembler "movapd.*\[bs\]p" } } */
+/* { dg-final { scan-assembler "movapd.*magic" } } */
 
 /* Verify that we generate proper instruction with memory operand.  */
 
 #include <xmmintrin.h>
+
+__m128d magic_a, magic_b;
+
 __m128d
-t1(__m128d a, __m128d b)
+t1(void)
 {
-return _mm_and_pd (a,b);
+return _mm_and_pd (magic_a,magic_b);
 }
 __m128d
-t2(__m128d a, __m128d b)
+t2(void)
 {
-return _mm_andnot_pd (a,b);
+return _mm_andnot_pd (magic_a,magic_b);
 }
 __m128d
-t3(__m128d a, __m128d b)
+t3(void)
 {
-return _mm_or_pd (a,b);
+return _mm_or_pd (magic_a,magic_b);
 }
 __m128d
-t4(__m128d a, __m128d b)
+t4(void)
 {
-return _mm_xor_pd (a,b);
+return _mm_xor_pd (magic_a,magic_b);
 }
diff --git a/gcc/testsuite/gcc.dg/i386-ssetype-2.c b/gcc/testsuite/gcc.dg/i386-ssetype-2.c
index b66aa0cfd98..1f9bedd0220 100644
--- a/gcc/testsuite/gcc.dg/i386-ssetype-2.c
+++ b/gcc/testsuite/gcc.dg/i386-ssetype-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler "andpd" } } */
 /* { dg-final { scan-assembler "andnpd" } } */
 /* { dg-final { scan-assembler "xorpd" } } */
diff --git a/gcc/testsuite/gcc.dg/i386-ssetype-3.c b/gcc/testsuite/gcc.dg/i386-ssetype-3.c
index 4988c0c5abd..bbc6f823bd9 100644
--- a/gcc/testsuite/gcc.dg/i386-ssetype-3.c
+++ b/gcc/testsuite/gcc.dg/i386-ssetype-3.c
@@ -1,32 +1,34 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
-/* { dg-final { scan-assembler "andps.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "andnps.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "xorps.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "orps.*\[bs\]p" } } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "andps.*magic" } } */
+/* { dg-final { scan-assembler "andnps.*magic" } } */
+/* { dg-final { scan-assembler "xorps.*magic" } } */
+/* { dg-final { scan-assembler "orps.*magic" } } */
 /* { dg-final { scan-assembler-not "movdqa" } } */
-/* { dg-final { scan-assembler "movaps.*\[bs\]p" } } */
+/* { dg-final { scan-assembler "movaps.*magic" } } */
 
 /* Verify that we generate proper instruction with memory operand.  */
 
 #include <xmmintrin.h>
+
+__m128 magic_a, magic_b;
 __m128
-t1(__m128 a, __m128 b)
+t1(void)
 {
-return _mm_and_ps (a,b);
+return _mm_and_ps (magic_a,magic_b);
 }
 __m128
-t2(__m128 a, __m128 b)
+t2(void)
 {
-return _mm_andnot_ps (a,b);
+return _mm_andnot_ps (magic_a,magic_b);
 }
 __m128
-t3(__m128 a, __m128 b)
+t3(void)
 {
-return _mm_or_ps (a,b);
+return _mm_or_ps (magic_a,magic_b);
 }
 __m128
-t4(__m128 a, __m128 b)
+t4(void)
 {
-return _mm_xor_ps (a,b);
+return _mm_xor_ps (magic_a,magic_b);
 }
diff --git a/gcc/testsuite/gcc.dg/i386-ssetype-4.c b/gcc/testsuite/gcc.dg/i386-ssetype-4.c
index ef6a93f6c16..e9d989ba974 100644
--- a/gcc/testsuite/gcc.dg/i386-ssetype-4.c
+++ b/gcc/testsuite/gcc.dg/i386-ssetype-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
 /* { dg-final { scan-assembler "andps" } } */
 /* { dg-final { scan-assembler "andnps" } } */
 /* { dg-final { scan-assembler "xorps" } } */
diff --git a/gcc/testsuite/gcc.dg/i386-ssetype-5.c b/gcc/testsuite/gcc.dg/i386-ssetype-5.c
index 97cc22fd3a8..31a8b9981e8 100644
--- a/gcc/testsuite/gcc.dg/i386-ssetype-5.c
+++ b/gcc/testsuite/gcc.dg/i386-ssetype-5.c
@@ -1,33 +1,34 @@
 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O2 -msse2 -march=athlon" } */
-/* { dg-final { scan-assembler "pand.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "pandn.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "pxor.*\[bs\]p" } } */
-/* { dg-final { scan-assembler "por.*\[bs\]p" } } */
+/* { dg-options "-O2 -msse2 -march=k8" } */
+/* { dg-final { scan-assembler "pand.*magic" } } */
+/* { dg-final { scan-assembler "pandn.*magic" } } */
+/* { dg-final { scan-assembler "pxor.*magic" } } */
+/* { dg-final { scan-assembler "por.*magic" } } */
 /* { dg-final { scan-assembler "movdqa" } } */
-/* { dg-final { scan-assembler-not "movaps.*\[bs\]p" } } */
+/* { dg-final { scan-assembler-not "movaps.*magic" } } */
 
 /* Verify that we generate proper instruction with memory operand.  */
 
 #include <xmmintrin.h>
+__m128i magic_a, magic_b;
 __m128i
-t1(__m128i a, __m128i b)
+t1(void)
 {
-return _mm_and_si128 (a,b);
+return _mm_and_si128 (magic_a,magic_b);
 }
 __m128i
-t2(__m128i a, __m128i b)
+t2(void)
 {
-return _mm_andnot_si128 (a,b);
+return _mm_andnot_si128 (magic_a,magic_b);
 }
 __m128i
-t3(__m128i a, __m128i b)
+t3(void)
 {
-return _mm_or_si128 (a,b);
+return _mm_or_si128 (magic_a,magic_b);
 }
 __m128i
-t4(__m128i a, __m128i b)
+t4(void)
 {
-return _mm_xor_si128 (a,b);
+return _mm_xor_si128 (magic_a,magic_b);
 }