From: Alec Roelke Date: Fri, 5 Jan 2018 00:04:43 +0000 (-0500) Subject: arch-riscv: Correct syscall argument reg count X-Git-Tag: v19.0.0.0~2406 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b001475a1ff5d4693f4d8b9063b3d602f7dd8043;p=gem5.git arch-riscv: Correct syscall argument reg count As per the discussion in patch #6904 and the Linux 4.15 kernel code for RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0 through a6), with x17 (a7) being used for the system call number. Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809 Reviewed-on: https://gem5-review.googlesource.com/7081 Reviewed-by: Jason Lowe-Power Reviewed-by: Tuan Ta Maintainer: Alec Roelke --- diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 01e385957..a61554c13 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -97,6 +97,10 @@ const std::vector ReturnValueRegs = {10, 11}; const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; const int AMOTempReg = 32; +const int SyscallPseudoReturnReg = 10; +const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16}; +const int SyscallNumReg = 17; + const std::vector IntRegNames = { "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", @@ -118,10 +122,6 @@ const std::vector FloatRegNames = { "ft8", "ft9", "ft10", "ft11" }; -const int SyscallNumReg = 17; -const std::vector SyscallArgumentRegs = {10, 11, 12, 13}; -const int SyscallPseudoReturnReg = 10; - enum MiscRegIndex { MISCREG_USTATUS = 0x000, MISCREG_UIE = 0x004,