From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Oct 2018 06:43:51 +0000 (+0100)
Subject: sv addw variable elwidth unit test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b004ad39b307505fb5a53c620d773cab8af1d88d;p=riscv-tests.git

sv addw variable elwidth unit test
---

diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv
index aaa7353..86b85fb 100644
--- a/isa/rv64ui/Makefrag.sv
+++ b/isa/rv64ui/Makefrag.sv
@@ -9,6 +9,7 @@ rv64ui_sv_tests = \
 	sv_addi_vector_vector \
 	sv_addi_predicated \
 	sv_add_elwidth \
+	sv_addw_elwidth \
 	sv_beq \
 
 rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests))
diff --git a/isa/rv64ui/sv_addw_elwidth.S b/isa/rv64ui/sv_addw_elwidth.S
new file mode 100644
index 0000000..0bfcfd0
--- /dev/null
+++ b/isa/rv64ui/sv_addw_elwidth.S
@@ -0,0 +1,73 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+#define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2 ) \
+                                                        \
+        SV_LDD_DATA( x4, testdata   , 0);               \
+        SV_LDD_DATA( x5, testdata+8 , 0);               \
+        SV_LDD_DATA( x12, testdata+16, 0);               \
+        SV_LDD_DATA( x13, testdata+24, 0);               \
+                                                        \
+        li x14, 0;                                      \
+        li x15, 0;                                      \
+                                                        \
+        SET_SV_MVL( 2);                                  \
+        SET_SV_3CSRS( SV_REG_CSR( 1, 4, wid1, 4, 1),       \
+                      SV_REG_CSR( 1, 12, wid2, 12, 1),        \
+                      SV_REG_CSR( 1, 14, wid3, 14, 1));       \
+        SET_SV_VL( 2);                                   \
+                                                        \
+        addw   x14, x4, x12;                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
+                                                        \
+        TEST_SV_IMM( x14, expect1 );                         \
+        TEST_SV_IMM( x15, expect2 );                       \
+        TEST_SV_IMM( x12, 0x0000005242322212);                       \
+        TEST_SV_IMM( x13, 0x0000005141312111);
+
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        # 
+        SV_ELWIDTH_TEST(  0, 0, 0, 0xffffffff8b6bab8b,  0xffffffff88684828 )
+        SV_ELWIDTH_TEST(  0, 0, 3, 0x886848288b6bab8b,  0x0000000000000000 )
+        SV_ELWIDTH_TEST(  1, 1, 0, 0xffffffffffffff8b,  0xffffffffffffffab )
+        SV_ELWIDTH_TEST(  1, 1, 3, 0xffffffabffffff8b,  0x0000000000000000 )
+        SV_ELWIDTH_TEST(  1, 1, 2, 0xffffffffffabff8b,  0x0000000000000000 )
+        SV_ELWIDTH_TEST(  1, 1, 1, 0xffffffffffffab8b,  0x0000000000000000 )
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 0x0000005949398979
+        .dword 0x0000005747372717
+        .dword 0x0000005242322212
+        .dword 0x0000005141312111
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+