From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 22 Mar 2023 20:49:30 +0000 (-0700)
Subject: add "Special Registers altered" sections
X-Git-Tag: opf_rfc_ls001_v3~111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b00624c34f66483b5e8048387ffacb2ce224246b;p=libreriscv.git

add "Special Registers altered" sections

I can't read the commitdiff of d827d9e11ce635d52652f8936a454319fa2ebea9,
so I'm reverting and reapplying it as a set of split-up commits.
---

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 8310d5592..d46ce05f3 100644
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -149,6 +149,10 @@ copying bits, `FPSCR` is not affected in any way.
 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
 operations.
 
+Special Registers altered:
+
+    CR1     (if Rc=1)
+
 ### Assembly Aliases
 
 | Assembly Alias    | Full Instruction   |
@@ -186,6 +190,10 @@ or equivalent to `std` followed by `lfd`. As `fmvfg` is just copying bits,
 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
 operations.
 
+Special Registers altered:
+
+    CR1     (if Rc=1)
+
 ### Assembly Aliases
 
 | Assembly Alias    | Full Instruction   |
@@ -254,6 +262,11 @@ as usual.
 Rc=1 tests FRT and sets CR1, exactly like all other Scalar Floating-Point
 operations.
 
+Special Registers altered:
+
+    CR1     (if Rc=1)
+    FPCSR   (TODO: which bits?)
+
 ### Assembly Aliases
 
 | Assembly Alias       | Full Instruction       |
@@ -551,6 +564,11 @@ NaN) then this is considered to be an integer Overflow condition, and
 CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
 that overflow.
 
+Special Registers altered:
+
+    CR0              (if Rc=1)
+    XER SO, OV, OV32 (if OE=1)
+
 ----------
 
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