From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 10 Jul 2019 08:37:32 +0000 (+0200)
Subject: soc_core: use fixed 16MB CSR address space
X-Git-Tag: 24jan2021_ls180~1112
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0192e5f8bb6f1d97a2d023bbf9f947b77c19c8c;p=litex.git

soc_core: use fixed 16MB CSR address space

Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 0e0a3017..5de233c7 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -298,7 +298,8 @@ class SoCCore(Module):
         self.add_csr_master(self.wishbone2csr.csr)
         self.config["CSR_DATA_WIDTH"] = csr_data_width
         self.config["CSR_ALIGNMENT"] = csr_alignment
-        self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))
+        assert 2**(csr_address_width + 2) <= 0x1000000
+        self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
 
         # Add UART
         if with_uart: