From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 May 2020 18:07:52 +0000 (+0200)
Subject: cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
X-Git-Tag: 24jan2021_ls180~399
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b02053357c22cd8e5595a024f2afb2b9363a85b3;p=litex.git

cpu/vexriscv: fix flush_cpu_icache, remove workaround on boot.c.
---

diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
index 952b5b32..a8fbe42b 100644
--- a/litex/soc/cores/cpu/vexriscv/system.h
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -10,7 +10,7 @@ extern "C" {
 __attribute__((unused)) static void flush_cpu_icache(void)
 {
   asm volatile(
-    ".word(0x400F)\n"
+    ".word(0x100F)\n"
     "nop\n"
     "nop\n"
     "nop\n"
diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 08b3be4a..8f53fcca 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -43,10 +43,7 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 	irq_setmask(0);
 	irq_setie(0);
 #endif
-/* FIXME: understand why flushing icache on Vexriscv make boot fail  */
-#ifndef __vexriscv__
 	flush_cpu_icache();
-#endif
 	flush_cpu_dcache();
 #ifdef CONFIG_L2_SIZE
 	flush_l2_cache();