From: lkcl <lkcl@web>
Date: Sat, 18 Jun 2022 11:25:09 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1720
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b02f58c92596ffd757f453608ca808be05241781;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index c6ad546f8..dda543680 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -167,9 +167,16 @@ Scalar instructions, stand on their own merit. Considerable
 lengths have been made to provide justifications for each of these
 *Scalar* instructions.
 
+Some of these Scalar instructions are specifically designed to make
+Scalable Vector binaries more efficient (less instructions) such
+as the crweird group.  Others are to bring the Scalar Power ISA
+up-to-date within specific workloads,
+such as a Javascript Rounding instruction. None of them are strictly
+necessary but performance and power consumption may be conpromised
+in certain workloads and use-cases without them.
+
 Vector-related:
 
-* [[sv/vector_swizzle]]
 * [[sv/mv.swizzle]] vec2/3/4 Swizzles (RGBA, XYZW) for 3D and CUDA.
   designed as a Scalar instruction.
 * [[sv/vector_ops]] scalar operations needed for supporting vectors
@@ -183,7 +190,8 @@ Scalar Instructions:
 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
-* Twin targetted instructions (two registers out, one implicit)
+* Twin targetted instructions (two registers out, one implicit, just like
+  Load-with-Update).
   Explanation of the rules for twin register targets
   (implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
   - [[isa/svfixedarith]]