From: lkcl <lkcl@web>
Date: Sat, 22 Oct 2022 16:41:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b03132a8023aa8fd4603c4e7e9fa52f317fffb77;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 46a421a95..8ff2396d9 100644
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -63,8 +63,12 @@ is Z23-Form in "overwrite" on RT.
 Both instructions take two 64-bit sources, concatenate
 them together then extract 64 bits from it, the offset
 location determined by a third source.  So as to avoid
-costly 4-reg (VA-Form) a 2-bit mode `sm` gives four
-potential overwrite and zero-source options instead.
+costly 4-reg (VA-Form) and to allow Vectorised versions
+to use EXTRA3 a 2-bit mode `sm` gives four
+potential overwrite and zero-source options instead
+(a 4-reg VA-Form Vector variant would use EXTRA2,
+limiting the vector offset range and preventing its
+use in biginteger vector-shift operations).
 
 # maddedu