From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 12:31:47 +0000 (+0200)
Subject: Added RTLIL::Module::connect(const RTLIL::SigSig&)
X-Git-Tag: yosys-0.4~419
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b03aec6e3212a387e3d255583476d472d16663f1;p=yosys.git

Added RTLIL::Module::connect(const RTLIL::SigSig&)
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 2378e95c5..ce4ecea6f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -873,6 +873,11 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 	return a->port_id < b->port_id;
 }
 
+void RTLIL::Module::connect(const RTLIL::SigSig &conn)
+{
+	connections_.push_back(conn);
+}
+
 void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
 {
 	connections_.push_back(RTLIL::SigSig(lhs, rhs));
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a2320873a..4f91b720d 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -288,6 +288,7 @@ struct RTLIL::Module
 	virtual void check();
 	virtual void optimize();
 
+	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
 	void fixup_ports();