From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 8 Nov 2013 04:20:15 +0000 (+0100)
Subject: Fixed keep attribute on wires in opt_clean
X-Git-Tag: yosys-0.2.0~380
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b04051a0e2f859c0d9f11109e8e05e9740438f9b;p=yosys.git

Fixed keep attribute on wires in opt_clean
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 8e3691b34..2921c92d8 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -54,7 +54,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 
 	for (auto &it : module->wires) {
 		RTLIL::Wire *wire = it.second;
-		if (wire->port_output) {
+		if (wire->port_output || wire->get_bool_attribute("\\keep")) {
 			std::set<RTLIL::Cell*> cell_list;
 			RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
 			assign_map.apply(sig);