From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 5 Oct 2020 23:16:46 +0000 (+0100)
Subject: add debug / investigation print statements
X-Git-Tag: 24jan2021_ls180~226
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b0450cfa6f2caf01756e9a1b6622832181af9b10;p=soc.git

add debug / investigation print statements
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 5f96e04a..732e9f3a 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -121,7 +121,7 @@ layout = """\
   .. --------|              | TAG_BITS      (45)
 """
 print (layout)
-print ("Dcache TAG %d IDX %d ROW %d ROFF %d LOFF %d RLB %d" % \
+print ("Dcache TAG %d IDX %d ROW_BITS %d ROFF %d LOFF %d RLB %d" % \
             (TAG_BITS, INDEX_BITS, ROW_BITS,
              ROW_OFF_BITS, LINE_OFF_BITS, ROW_LINE_BITS))
 print ("index @: %d-%d" % (LINE_OFF_BITS, SET_SIZE_BITS))
@@ -130,6 +130,8 @@ print ("tag @: %d-%d width %d" % (SET_SIZE_BITS, REAL_ADDR_BITS, TAG_WIDTH))
 
 TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS
 
+print ("TAG_RAM_WIDTH", TAG_RAM_WIDTH)
+
 def CacheTagArray():
     return Array(Signal(TAG_RAM_WIDTH, name="cachetag_%d" % x) \
                         for x in range(NUM_LINES))