From: Luke Kenneth Casson Leighton Date: Tue, 4 Dec 2018 08:04:44 +0000 (+0000) Subject: record conversation snippet X-Git-Tag: convert-csv-opcode-to-binary~4814 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b04598c4d1ead4ddacb7042b17a60c64d934827a;p=libreriscv.git record conversation snippet --- diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn index d22e36e76..150635dd0 100644 --- a/3d_gpu/microarchitecture.mdwn +++ b/3d_gpu/microarchitecture.mdwn @@ -156,10 +156,10 @@ because actual updating of memory occurs in order, when a store is at the head of the ROB, and hence, no earlier loads or stores can still be pending * RAW hazards are maintained by two restrictions: - 1. not allowing a load to initiate the second step of its execution if - any active ROB entry occupied by a store has a destination - field that matches the value of the A field of the load and - 2. maintaining the program order for the computation of an effective + 1. not allowing a load to initiate the second step of its execution if + any active ROB entry occupied by a store has a destination + field that matches the value of the A field of the load and + 2. maintaining the program order for the computation of an effective address of a load with respect to all earlier stores * These restrictions ensure that any load that access a memory location written to by an earlier store cannot perform the memory access until