From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 4 Jan 2019 16:20:49 +0000 (+0000)
Subject: cpu: Fix VecElemClass bugs in cpu models
X-Git-Tag: v19.0.0.0~1221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b045de7e6969d5a40d4a3f9b178844cc911ac4c2;p=gem5.git

cpu: Fix VecElemClass bugs in cpu models

This patch is:

* Adding a missing VecElemClass entry
* Fixing assertion in rename map which was checking the number of free
  vector registers rather than free vector element registers
* Fixing assertion in read/setVecElemOperand APIs.
* Using the right register index in SimpleThread
* Using VecElem instead of VecReg on O3 readArchVecElem

Change-Id: I265320dcbe35eb47075991301dfc99333c5190c4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15598
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 76d46e905..b9ed3971f 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -157,7 +157,7 @@ class ExecContext : public ::ExecContext
     readVecElemOperand(const StaticInst *si, int idx) const override
     {
         const RegId& reg = si->srcRegIdx(idx);
-        assert(reg.isVecReg());
+        assert(reg.isVecElem());
         return thread.readVecElem(reg);
     }
 
@@ -268,7 +268,7 @@ class ExecContext : public ::ExecContext
                       const TheISA::VecElem val) override
     {
         const RegId& reg = si->destRegIdx(idx);
-        assert(reg.isVecReg());
+        assert(reg.isVecElem());
         thread.setVecElem(reg, val);
     }
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7261f0c9e..9e1efa179 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1410,7 +1410,7 @@ FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                                  ThreadID tid) const -> const VecElem&
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
-                                RegId(VecRegClass, reg_idx, ldx));
+                                RegId(VecElemClass, reg_idx, ldx));
     return readVecElem(phys_reg);
 }
 
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 3ad08ee98..e7a899cdf 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -234,6 +234,9 @@ class UnifiedFreeList
     /** Returns the number of free vector registers. */
     unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }
 
+    /** Returns the number of free vector registers. */
+    unsigned numFreeVecElems() const { return vecElemList.numFreeRegs(); }
+
     /** Returns the number of free cc registers. */
     unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
 };
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 4331b6d08..c5be40464 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1039,6 +1039,7 @@ DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
             fpRenameLookups++;
             break;
           case VecRegClass:
+          case VecElemClass:
             vecRenameLookups++;
             break;
           case CCRegClass:
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 1194b550b..d1876a965 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -161,7 +161,7 @@ UnifiedRenameMap::switchMode(VecMode newVecMode, UnifiedFreeList* freeList)
         /* The free list should currently be tracking register elems. */
         panic_if(freeList->hasFreeVecRegs(),
                 "The free list is already tracking full Vec");
-        panic_if(freeList->numFreeVecRegs() !=
+        panic_if(freeList->numFreeVecElems() !=
                 regFile->numVecElemPhysRegs() - TheISA::NumFloatRegs,
                 "The free list has lost vector register elements");
         /* To rebuild the arch regs we take the easy road:
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 7db7d20d9..cbca34123 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -317,7 +317,7 @@ class SimpleExecContext : public ExecContext {
     readVecElemOperand(const StaticInst *si, int idx) const override
     {
         numVecRegReads++;
-        const RegId& reg = si->destRegIdx(idx);
+        const RegId& reg = si->srcRegIdx(idx);
         assert(reg.isVecElem());
         return thread->readVecElem(reg);
     }