From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 15 Mar 2019 16:49:39 +0000 (+0100)
Subject: vexriscv/core: fix min variant
X-Git-Tag: 24jan2021_ls180~1363
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b04a756abb03cce48a1be84878c02c5a5bbe8b70;p=litex.git

vexriscv/core: fix min variant
---

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 1edcc3f7..3700bf44 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -155,8 +155,8 @@ class VexRiscv(Module, AutoCSR):
             "std_debug":  "VexRiscv_Debug.v",
             "lite":       "VexRiscv_Lite.v",
             "lite_debug": "VexRiscv_LiteDebug.v",
-            "min":        "VexRiscv_Lite.v",
-            "min_debug":  "VexRiscv_LiteDebug.v",
+            "min":        "VexRiscv_Min.v",
+            "min_debug":  "VexRiscv_MinDebug.v",
         }
         cpu_filename = verilog_variants[variant]
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")