From: lkcl <lkcl@web>
Date: Sat, 23 Jul 2022 09:49:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b04c16619565bb3a87486c46bef20b42e5c2da44;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index fb8d8714a..b2fef5825 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -1,4 +1,3 @@
-
 Simple-V is a Scalable Vector ISA Extension specifically for the Power ISA.
 It is extremely important to think of Simple-V as a 2-Dimensional ISA:
 instructions vertical and registers horizontal otherwise it will be
@@ -15,6 +14,12 @@ ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
 through explicit predicate masks which increases instruction count in
 hot-loops.
 
+**Simple-V does not modify harm or corrupt the existing Power ISA** and does not
+interfere with an existing system.  It needs only a small allocation of opcodes (five) to implement, whereas any other Vector implementation would
+require an intrusive fundamental overhaul of the Power ISA.
+
+We invented Simple-V to be simple because we don't like complicated.
+
 Links to Simulator and Unit tests:
 
 * Unit tests and simulator for Power ISA v3.0 and SVP64