From: Eric Anholt <eric@anholt.net>
Date: Thu, 13 Aug 2009 02:40:27 +0000 (-0700)
Subject: intel: Align untiled region height to 2 according to 965 docs.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b053474378633249be0e9f24010650ffb816229a;p=mesa.git

intel: Align untiled region height to 2 according to 965 docs.

This may or may not be required pre-965, but it doesn't seem unlikely, and
I'd rather be safe.
---

diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 497f7967649..068a3f33797 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -181,10 +181,20 @@ intel_region_alloc(struct intel_context *intel,
    dri_bo *buffer;
    struct intel_region *region;
 
+   /* If we're tiled, our allocations are in 8 or 32-row blocks, so
+    * failure to align our height means that we won't allocate enough pages.
+    *
+    * If we're untiled, we still have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
    if (tiling == I915_TILING_X)
       height = ALIGN(height, 8);
    else if (tiling == I915_TILING_Y)
       height = ALIGN(height, 32);
+   else
+      height = ALIGN(height, 2);
 
    if (expect_accelerated_upload) {
       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",