From: Marcelina Koƛcielnicka Date: Tue, 23 Feb 2021 20:23:26 +0000 (+0100) Subject: Add tests for some common techmap files. X-Git-Tag: working-ls180~39 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b05b98521c781fef0f9d900a53310cad9e1434b0;p=yosys.git Add tests for some common techmap files. --- diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys new file mode 100644 index 000000000..53f7d2f08 --- /dev/null +++ b/tests/techmap/adff2dff.ys @@ -0,0 +1,19 @@ +read_verilog -icells << EOT +module top(...); + +input [1:0] D; +input C, R; +output [1:0] Q; + +always @(posedge C, posedge R) + if (R) + Q <= 0; + else + Q <= D; + +endmodule +EOT + +proc + +equiv_opt -async2sync techmap -map +/adff2dff.v diff --git a/tests/techmap/dff2ff.ys b/tests/techmap/dff2ff.ys new file mode 100644 index 000000000..5adf14b07 --- /dev/null +++ b/tests/techmap/dff2ff.ys @@ -0,0 +1,16 @@ +read_verilog -icells << EOT +module top(...); + +input [1:0] D; +input C; +output [1:0] Q; + +always @(posedge C) + Q <= D; + +endmodule +EOT + +proc + +equiv_opt techmap -map +/dff2ff.v diff --git a/tests/techmap/pmux2mux.ys b/tests/techmap/pmux2mux.ys new file mode 100644 index 000000000..1714a6b87 --- /dev/null +++ b/tests/techmap/pmux2mux.ys @@ -0,0 +1,15 @@ +read_verilog -icells << EOT +module top(...); + +input [3:0] A; +input [3:0] B0; +input [3:0] B1; +input [1:0] S; +output [3:0] O; + +\$pmux #(.WIDTH(4), .S_WIDTH(2)) pm (.A(A), .B({B1, B0}), .S(S), .Y(O)); + +endmodule +EOT + +equiv_opt techmap -map +/pmux2mux.v