From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 Dec 2021 10:50:10 +0000 (+0100)
Subject: If direction NONE use that from first bit
X-Git-Tag: yosys-0.13~40^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b06f547993818224ded59c555345140199f4595f;p=yosys.git

If direction NONE use that from first bit
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index dccdcb482..0548d9cb1 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1112,6 +1112,13 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 		for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {
 			if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {
+				if (portbus->GetDir() == DIR_NONE && !wire->port_input && !wire->port_output)  {
+					Port *p = portbus->ElementAtIndex(i);
+					if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_IN)
+						wire->port_input = true;
+					if (p->GetDir() == DIR_INOUT || p->GetDir() == DIR_OUT)
+						wire->port_output = true;
+				}
 				net = portbus->ElementAtIndex(i)->GetNet();
 				RTLIL::SigBit bit(wire, i - wire->start_offset);
 				if (net_map.count(net) == 0)