From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Oct 2020 11:58:34 +0000 (+0100)
Subject: use unittest.TestCase rather than FHDLTestCase
X-Git-Tag: 24jan2021_ls180~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b07042bfb1132455a1e0b7d82c6dd47071c0df57;p=nmutil.git

use unittest.TestCase rather than FHDLTestCase
---

diff --git a/src/nmutil/test/test_clz.py b/src/nmutil/test/test_clz.py
index 1d066b4..09beb73 100644
--- a/src/nmutil/test/test_clz.py
+++ b/src/nmutil/test/test_clz.py
@@ -1,6 +1,5 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
 
 from nmutil.clz import CLZ
 import unittest
@@ -8,7 +7,7 @@ import math
 import random
 
 
-class CLZTestCase(FHDLTestCase):
+class CLZTestCase(unittest.TestCase):
     def run_test(self, inputs, width=8):
 
         m = Module()