From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jun 2018 22:32:02 +0000 (+0100)
Subject: update
X-Git-Tag: convert-csv-opcode-to-binary~5260
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b071dfd3614a8f5d91eee5a25c7bfcc1310b0ad9;p=libreriscv.git

update
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 18ae7b4cd..b72a5f61b 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -209,7 +209,8 @@
    \item SIMD ALU(s) primarily unchanged\vspace{6pt}
    \item Predication is added to each SIMD element\vspace{6pt}
    \item Predication bits sent in groups to the ALU\vspace{6pt}
-   \item End of Vector enables (additional) predication\vspace{10pt}
+   \item End of Vector enables (additional) predication\\
+	     (completely nullifies need for end-case code)
   \end{itemize}
   Considerations:\vspace{4pt}
    \begin{itemize}