From: Luke Kenneth Casson Leighton Date: Thu, 26 Jul 2018 05:18:39 +0000 (+0100) Subject: add num dma channels define X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b07bf3091e5b841d985249016285b0ec5185552d;p=pinmux.git add num dma channels define --- diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv index 6b2cc8e..c080251 100644 --- a/src/bsv/bsv_lib/soc_template.bsv +++ b/src/bsv/bsv_lib/soc_template.bsv @@ -31,6 +31,7 @@ package Soc; import slow_peripherals::*; `include "defines.bsv" `include "instance_defines.bsv" +{8} /*====== AXI4 slave declarations =======*/ {3} /*====== AXI4 Master declarations =======*/ @@ -121,7 +122,7 @@ package Soc; Ifc_TCM tcm <- mkTCM; `endif `ifdef DMA - DmaC#(7,12) dma <- mkDMA(); + DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA(); `endif `ifdef VME Ifc_vme_top vme <-mkvme_top(); diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 2094548..6bde207 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -1,5 +1,23 @@ import types +def li(txt, indent): + indent = ' ' * indent + istxt = False + if isinstance(txt, str): + istxt = True + txt = txt.split('\n') + res = [] + for line in txt: + line = line.split('\n') + res += line + txt = res + res = [] + for line in txt: + res.append(indent + line) + if istxt: + res = '\n'.join(res) + return res + class PBase(object): def __init__(self, name): @@ -26,8 +44,8 @@ class PBase(object): if not irqname: return '' pirqname = self.irq_name().format(count) - template = " {0}_interrupt.send(\n" + \ - " slow_peripherals.{1});" + template = " {0}_interrupt.send(\n" + \ + " slow_peripherals.{1});" return template.format(irqname, pirqname) def get_clock_reset(self, name, count): @@ -38,12 +56,15 @@ class PBase(object): if not irqname: return '' sname = self.peripheral.iname().format(count) - template = " SyncBitIfc#(Bit#(1)) {0} <-\n" + \ - " <-mkSyncBitToCC({1});" + template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \ + " <-mkSyncBitToCC({1});" return template.format(irqname, self.get_clock_reset(name, count)) def mk_dma_connect(self, name, count): - return '' + irqname = self.mk_dma_irq(name, count) + if not irqname: + return '' + return "{0}.read".format(irqname) def fastifdecl(self, name, count): return '' @@ -270,23 +291,34 @@ axi_master_declarations= """\ typedef 0 Dmem_master_num; typedef 1 Imem_master_num; {0} -typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif ) Debug_master_num; -typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) DMA_master_num; -typedef TAdd#(DMA_master_num,1) Num_Masters; +typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif ) + Debug_master_num; +typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) + DMA_master_num; +typedef TAdd#(DMA_master_num,1) + Num_Masters; """ axi_fastslave_declarations = """\ {0} typedef TAdd#(LastGen_fastslave_num,1) Sdram_cfg_slave_num; -typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif ) Sdram_cfg_slave_num; -typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif ) BootRom_slave_num ; -typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif ) Debug_slave_num ; -typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif ) TCM_slave_num; -typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif ) Dma_slave_num; +typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif ) + Sdram_cfg_slave_num; +typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif ) + BootRom_slave_num ; +typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif ) + Debug_slave_num ; +typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif ) + TCM_slave_num; +typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif ) + Dma_slave_num; typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num; -typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif ) VME_slave_num; -typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif ) FlexBus_slave_num; -typedef TAdd#(FlexBus_slave_num,1) Num_Slaves; +typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif ) + VME_slave_num; +typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif ) + FlexBus_slave_num; +typedef TAdd#(FlexBus_slave_num,1) + Num_Slaves; """ @@ -333,7 +365,7 @@ class PeripheralIface(object): 'extfastifinstance', 'extifinstance', 'extifdecl', 'slowifdecl', 'slowifdeclmux', 'fastifdecl', - 'mkslow_peripheral', + 'mkslow_peripheral', 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule', 'mkfast_peripheral', 'mk_plic', 'mk_ext_ifacedef', @@ -594,21 +626,29 @@ class PeripheralInterfaces(object): cnct.append(txt) ifacerules = list(filter(None, ifacerules)) if ifacerules: - txt = " rule synchronize_%s_interrupts;" % name + txt = "rule synchronize_%s_interrupts;" % name rules.append(txt) rules += ifacerules - rules.append(" endrule") + rules.append("endrule") + cnct = list(filter(None, cnct)) ct = self.dma_count - _cnct = [" rule rl_connect_interrupt_to_DMA;", - " Bit #(%d) lv_interrupt_to_DMA={" % ct] - cnct = _cnct + cnct - cnct.append(" };") - cnct.append(" dma.interrupt_from_peripherals(\n" + \ - " lv_interrupt_to_DMA);") - cnct.append(" endrule;") - - return '\n'.join(list(filter(None, sync + rules + cnct))) + _cnct = ["rule rl_connect_interrupt_to_DMA;", + " Bit #(%d) lv_interrupt_to_DMA={" % ct] + spc = " " + spcsep = ",\n" + spc + cnct = _cnct + [spc + spcsep.join(cnct)] + cnct.append(" };") + cnct.append(" dma.interrupt_from_peripherals(\n" + \ + " lv_interrupt_to_DMA);") + cnct.append("endrule;") + + ret = list(filter(None, sync + rules + cnct)) + ret = li(ret, 15) + return '\n'.join(ret) + + def num_dmachannels(self): + return "`define NUM_DMACHANNELS {0}".format(self.dma_count) def mk_ext_ifacedef(self): ret = [] diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 0011dd0..3a9a4a0 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -147,10 +147,11 @@ def write_soc(soc, soct, p, ifaces, iocells): numsloirqs = ifaces.mk_sloirqsdef() ifacedef = ifaces.mk_ext_ifacedef() dma = ifaces.mk_dma_irq() + num_dmachannels = ifaces.num_dmachannels() with open(soc, "w") as bsv_file: bsv_file.write(soct.format(imports, ifdecl, mkfast, slavedecl, mastdecl, mkcon, - inst, dma, + inst, dma, num_dmachannels, #'', '' #regdef, slavedecl, #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon, #pincon, inst, mkplic,